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Florence Azaïs: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand
    A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:383-387 [Conf]
  2. Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell
    TI-BIST: a temperature independent analog BIST for switched-capacitor filters. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:78-83 [Conf]
  3. Michel Renovell, Florence Azaïs, Yves Bertrand
    A design-for-test technique for multistage analog circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:113-119 [Conf]
  4. Michel Renovell, Florence Azaïs, J-C. Bodin, Yves Bertrand
    BISTing Switched-Current Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:372-377 [Conf]
  5. Michel Renovell, Jean Marc Galliere, Florence Azaïs, Yves Bertrand
    Delay Testing of MOS Transistor with Gate Oxide Short. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:168-173 [Conf]
  6. Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs
    Analysis and Attenuation Proposal in Ground Bounce. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:460-463 [Conf]
  7. Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell
    Implementation of a linear histogram BIST for ADCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:590-595 [Conf]
  8. Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski
    Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:226-0 [Conf]
  9. Michel Renovell, Florence Azaïs, Yves Bertrand
    Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:815-821 [Conf]
  10. Yves Bertrand, Marie-Lise Flottes, Florence Azaïs, Serge Bernard, Laurent Latorre, Regis Lorival
    European Network for Test Education. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:230-234 [Conf]
  11. Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell
    Analog BIST Generator for ADC Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:338-346 [Conf]
  12. Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell
    On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:425-436 [Conf]
  13. Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski
    Testing the Configurable Analog Blocks of Field Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:893-902 [Conf]
  14. Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell
    A New Methodology For ADC Test Flow Optimization. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:201-209 [Conf]
  15. Michel Renovell, Jean Marc Galliere, Florence Azaïs, Serge Bernard, Yves Bertrand
    Boolean and current detection of MOS transistor with gate oxide short. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1039-1048 [Conf]
  16. Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq
    Optimal conditions for Boolean and current detection of floating gate faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:477-486 [Conf]
  17. Yves Bertrand, Florence Azaïs, Marie-Lise Flottes, Regis Lorival
    A Successful Distance-Learning Experience for IC Test Education. [Citation Graph (0, 0)][DBLP]
    MSE, 1999, pp:20-21 [Conf]
  18. Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell
    A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:266-271 [Conf]
  19. Florence Azaïs, Michel Renovell, Yves Bertrand, J-C. Bodin
    Design-For-Testability for Switched-Current Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:370-375 [Conf]
  20. Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell
    An Approach to the Built-In Self-Test of Field Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:383-388 [Conf]
  21. N. Dumas, Florence Azaïs, Laurent Latorre, Pascal Nouet
    On-Chip Electro-Thermal Stimulus Generation for a MEMS-Based Magnetic Field Sensor. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:213-218 [Conf]
  22. Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell
    Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:389-394 [Conf]
  23. Michel Renovell, Florence Azaïs, Yves Bertrand
    The multi-configuration: A DFT technique for analog circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:54-59 [Conf]
  24. Michel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand
    Hardware Resource Minimization for Histogram-Based ADC BIST. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:247-254 [Conf]
  25. Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei
    An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:60-67 [Journal]
  26. Uros Kac, Franc Novak, Florence Azaïs, Pascal Nouet, Michel Renovell
    Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:2, pp:32-39 [Journal]
  27. Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
    A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:3, pp:234-243 [Journal]
  28. Michel Renovell, Florence Azaïs, Yves Bertrand
    Improving Defect Detection in Static-Voltage Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:6, pp:83-89 [Journal]
  29. Jean Marc Galliere, Michel Renovell, Florence Azaïs, Yves Bertrand
    Delay Testing Viability of Gate Oxide Short Defects. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:195-200 [Journal]
  30. André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand
    On the detectability of CMOS floating gate transistor faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:116-128 [Journal]
  31. Florence Azaïs, B. Caillard, S. Dournelle, P. Salomé, Pascal Nouet
    A new multi-finger SCR-based structure for efficient on-chip ESD protection. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:233-243 [Journal]
  32. Christophe Entringer, Philippe Flatresse, Philippe Galy, Florence Azaïs, Pascal Nouet
    Electro-thermal short pulsed simulation for SOI technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:9-11, pp:1482-1485 [Journal]
  33. Antonio Andrade Jr., Gustavo Vieira, Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell
    Built-in self-test of global interconnects of field programmable analog arrays. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:12, pp:1112-1123 [Journal]
  34. Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
    "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:211-216 [Conf]
  35. Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
    "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:159-164 [Conf]
  36. Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell
    A-to-D converters static error detection from dynamic parameter measurement. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:10, pp:945-953 [Journal]
  37. Tiago R. Balen, Antonio Q. Andrade, Florence Azaïs, Marcelo Lubaszewski, Michel Renovell
    Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:2, pp:135-146 [Journal]
  38. Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell
    Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:291-298 [Journal]
  39. Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell
    A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:1, pp:9-16 [Journal]
  40. N. Dumas, Florence Azaïs, Laurent Latorre, Pascal Nouet
    Electro-thermal Stimuli for MEMS Testing in FSBM Technology. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:2, pp:189-198 [Journal]

  41. Exploiting Zero-Crossing for the Analysis of FM Modulated Analog/RF Signals Using Digital ATE. [Citation Graph (, )][DBLP]


  42. On-chip analog output response compaction. [Citation Graph (, )][DBLP]


  43. A novel method for test and calibration of capacitive accelerometers with a fully electrical setup. [Citation Graph (, )][DBLP]


  44. An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. [Citation Graph (, )][DBLP]


  45. On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring. [Citation Graph (, )][DBLP]


  46. On the use of standard digital ATE for the analysis of RF signals. [Citation Graph (, )][DBLP]


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