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Michel Renovell: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand
    A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:383-387 [Conf]
  2. Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell
    TI-BIST: a temperature independent analog BIST for switched-capacitor filters. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:78-83 [Conf]
  3. S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault
    Test configurations to enhance the testability of sequential circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:160-168 [Conf]
  4. Sumbal Rafiq, André Ivanov, Sassan Tabatabaei, Michel Renovell
    Testing for Floating Gates Defects in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:228-236 [Conf]
  5. Michel Renovell
    Microsystems Testing: A Challenge. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:512- [Conf]
  6. Michel Renovell, Florence Azaïs, Yves Bertrand
    A design-for-test technique for multistage analog circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:113-119 [Conf]
  7. Michel Renovell, Florence Azaïs, J-C. Bodin, Yves Bertrand
    BISTing Switched-Current Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:372-377 [Conf]
  8. Michel Renovell, Jean Marc Galliere, Florence Azaïs, Yves Bertrand
    Delay Testing of MOS Transistor with Gate Oxide Short. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:168-173 [Conf]
  9. Michel Renovell, P. Huc, Yves Bertrand
    Serial transistor network modeling for bridging fault simulation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:100-106 [Conf]
  10. Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
    TOF: a tool for test pattern generation optimization of an FPGA application oriented test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:323-328 [Conf]
  11. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:254-0 [Conf]
  12. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:266-271 [Conf]
  13. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    Minimizing the Number of Test Configurations for Different FPGA Families. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:363-368 [Conf]
  14. Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs
    Analysis and Attenuation Proposal in Ground Bounce. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:460-463 [Conf]
  15. Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell
    Implementation of a linear histogram BIST for ADCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:590-595 [Conf]
  16. Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski
    Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:226-0 [Conf]
  17. Cecilia Metra, Michel Renovell, G. Mojoli, Jean Michel Portal, S. Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi
    Novel Technique for Testing FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:89-0 [Conf]
  18. Michel Renovell, Florence Azaïs, Yves Bertrand
    Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:815-821 [Conf]
  19. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    RAM-Based FPGA's: A Test Approach for the Configurable Logic. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:82-88 [Conf]
  20. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:618-622 [Conf]
  21. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
    High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:83-88 [Conf]
  22. Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell
    Electrical Behavior of GOS Fault affected Domino Logic Cell. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:183-189 [Conf]
  23. Michel Renovell, Penelope Faure, Paolo Prinetto, Yervant Zorian
    Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:297-301 [Conf]
  24. Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell
    Analog BIST Generator for ADC Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:338-346 [Conf]
  25. Michel Renovell, Joan Figueras
    Current Testing Viability in Dynamic CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:207-214 [Conf]
  26. Michel Renovell, P. Huc, Yves Bertrand
    The Configuration Ratio: A Model for Simulating CMOS Intra-Gate Bridge with Variable Logic Thresholds. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:165-177 [Conf]
  27. Michel Renovell, P. Huc, Yves Bertrand
    The Logic Threshold Based Voting: A Model for Local Feedback Bridging Fault. [Citation Graph (0, 0)][DBLP]
    EDCC, 1996, pp:205-213 [Conf]
  28. Michel Renovell
    A Specific Test Methodology for Symmetric SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:300-311 [Conf]
  29. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:139-148 [Conf]
  30. Karl-Erwin Großpietsch, Jacob A. Abraham, Johannes Maier, Hans-Dieter Kochs, Michel Renovell
    From Dependable Computing Systems to Computing for Integrated Dependable Systems? (Panel). [Citation Graph (0, 0)][DBLP]
    FTCS, 1998, pp:296-301 [Conf]
  31. Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell
    On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:425-436 [Conf]
  32. David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell
    Scan Design and Secure Chip. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:219-226 [Conf]
  33. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
    Defect Analysis for Delay-Fault BIST in FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:124-128 [Conf]
  34. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
    BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:187-192 [Conf]
  35. Michel Renovell
    Revisiting the Classical Fault Models through a Detailed Analysis of Realistic Defects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:359-364 [Conf]
  36. Tiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell
    Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:192-197 [Conf]
  37. Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski
    Testing the Configurable Analog Blocks of Field Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:893-902 [Conf]
  38. Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell
    A New Methodology For ADC Test Flow Optimization. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:201-209 [Conf]
  39. Yves Bertrand, Frédéric Bancel, Michel Renovell
    Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:989-997 [Conf]
  40. Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
    Simulating Resistive Bridging and Stuck-At Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1051-1059 [Conf]
  41. Michel Renovell, Yves Bertrand
    Test Strategy Sensitivity to Defect Parameters. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:607-616 [Conf]
  42. Michel Renovell, Penelope Faure, Jean Michel Portal, Joan Figueras, Yervant Zorian
    IS-FPGA : a new symmetric FPGA architecture with implicit scan. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:924-931 [Conf]
  43. Michel Renovell, Jean Marc Galliere, Florence Azaïs, Serge Bernard, Yves Bertrand
    Boolean and current detection of MOS transistor with gate oxide short. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1039-1048 [Conf]
  44. Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq
    Optimal conditions for Boolean and current detection of floating gate faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:477-486 [Conf]
  45. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    SRAM-based FPGA's: testing the LUT/RAM modules. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:1102-1111 [Conf]
  46. Michel Renovell, Yervant Zorian
    Different experiments in test generation for XILINX FPGAs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:854-862 [Conf]
  47. Yves Bertrand, Frédéric Bancel, Michel Renovell
    A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:51-54 [Conf]
  48. Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell
    A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:266-271 [Conf]
  49. Florence Azaïs, Michel Renovell, Yves Bertrand, J-C. Bodin
    Design-For-Testability for Switched-Current Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:370-375 [Conf]
  50. Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell
    An Approach to the Built-In Self-Test of Field Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:383-388 [Conf]
  51. Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell
    Functional Test of Field Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:326-333 [Conf]
  52. Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
    The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:171-178 [Conf]
  53. Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell
    Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:389-394 [Conf]
  54. Ilia Polian, Sandip Kundu, Jean Marc Galliere, Piet Engelke, Michel Renovell, Bernd Becker
    Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:343-348 [Conf]
  55. Michel Renovell, Florence Azaïs, Yves Bertrand
    The multi-configuration: A DFT technique for analog circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:54-59 [Conf]
  56. Michel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand
    Hardware Resource Minimization for Histogram-Based ADC BIST. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:247-254 [Conf]
  57. Michel Renovell, Joan Figueras, Yervant Zorian
    Test of RAM-based FPGA: methodology and application to the interconnect. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:230-237 [Conf]
  58. Michel Renovell, P. Huc, Yves Bertrand
    The concept of resistance interval: a new parametric model for realistic resistive bridging fault. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:184-189 [Conf]
  59. Michel Renovell, P. Huc, Yves Bertrand
    Bridging fault coverage improvement by power supply control. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:338-343 [Conf]
  60. Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure
    A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:154-170 [Conf]
  61. Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei
    An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:60-67 [Journal]
  62. Uros Kac, Franc Novak, Florence Azaïs, Pascal Nouet, Michel Renovell
    Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:2, pp:32-39 [Journal]
  63. Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
    A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:3, pp:234-243 [Journal]
  64. Michel Renovell, Florence Azaïs, Yves Bertrand
    Improving Defect Detection in Static-Voltage Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:6, pp:83-89 [Journal]
  65. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    Testing the Interconnect of RAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:45-50 [Journal]
  66. Michel Renovell
    Some Aspects of the Test Generation Problem for an Application-Oriented Test of SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2003, v:12, n:2, pp:143-158 [Journal]
  67. Jean Marc Galliere, Michel Renovell, Florence Azaïs, Yves Bertrand
    Delay Testing Viability of Gate Oxide Short Defects. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:195-200 [Journal]
  68. Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
    Simulating Resistive-Bridging and Stuck-At Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2181-2192 [Journal]
  69. André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand
    On the detectability of CMOS floating gate transistor faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:116-128 [Journal]
  70. Michel Renovell, Gaston Cambon
    Electrical analysis and modeling of floating-gate fault. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1450-1458 [Journal]
  71. Antonio Andrade Jr., Gustavo Vieira, Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell
    Built-in self-test of global interconnects of field programmable analog arrays. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:12, pp:1112-1123 [Journal]
  72. Philippe Cauvet, Serge Bernard, Michel Renovell
    System-in-Package, a Combination of Challenges and Solutions. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:193-199 [Conf]
  73. Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
    "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:211-216 [Conf]
  74. Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
    "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:159-164 [Conf]
  75. Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell
    A-to-D converters static error detection from dynamic parameter measurement. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:10, pp:945-953 [Journal]
  76. Adoración Rueda, Michel Renovell, José Luis Huertas
    Guest Editorial. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:203- [Journal]
  77. Tiago R. Balen, Antonio Q. Andrade, Florence Azaïs, Marcelo Lubaszewski, Michel Renovell
    Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:2, pp:135-146 [Journal]
  78. Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell
    Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:291-298 [Journal]
  79. Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell
    A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:1, pp:9-16 [Journal]
  80. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
    Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:1, pp:43-55 [Journal]
  81. Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
    Modeling Feedback Bridging Faults with Non-Zero Resistance. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:1, pp:57-69 [Journal]
  82. Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
    Automatic Test Pattern Generation for Resistive Bridging Faults. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:1, pp:61-69 [Journal]
  83. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
    An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:2, pp:161-172 [Journal]

  84. On-chip analog output response compaction. [Citation Graph (, )][DBLP]


  85. An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. [Citation Graph (, )][DBLP]


  86. On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring. [Citation Graph (, )][DBLP]


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