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Yves Bertrand :
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Florence Azaïs , André Ivanov , Michel Renovell , Yves Bertrand A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1998, pp:383-387 [Conf ] Luigi Carro , Érika F. Cota , Marcelo Lubaszewski , Yves Bertrand , Florence Azaïs , Michel Renovell TI-BIST: a temperature independent analog BIST for switched-capacitor filters. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2000, pp:78-83 [Conf ] S. Lavabre , Yves Bertrand , Michel Renovell , Christian Landrault Test configurations to enhance the testability of sequential circuits. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1995, pp:160-168 [Conf ] Michel Renovell , Florence Azaïs , Yves Bertrand A design-for-test technique for multistage analog circuits. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1995, pp:113-119 [Conf ] Michel Renovell , Florence Azaïs , J-C. Bodin , Yves Bertrand BISTing Switched-Current Circuits. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1998, pp:372-377 [Conf ] Michel Renovell , Jean Marc Galliere , Florence Azaïs , Yves Bertrand Delay Testing of MOS Transistor with Gate Oxide Short. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2003, pp:168-173 [Conf ] Michel Renovell , P. Huc , Yves Bertrand Serial transistor network modeling for bridging fault simulation. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1995, pp:100-106 [Conf ] Florence Azaïs , Serge Bernard , Yves Bertrand , Michel Renovell Implementation of a linear histogram BIST for ADCs. [Citation Graph (0, 0)][DBLP ] DATE, 2001, pp:590-595 [Conf ] Vincent Beroulle , Yves Bertrand , Laurent Latorre , Pascal Nouet On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:1120- [Conf ] Érika F. Cota , Michel Renovell , Florence Azaïs , Yves Bertrand , Luigi Carro , Marcelo Lubaszewski Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. [Citation Graph (0, 0)][DBLP ] DATE, 2000, pp:226-0 [Conf ] Laurent Latorre , Yves Bertrand , P. Hazard , F. Pressecq , Pascal Nouet Design, Characterization & Modelling of a CMOS Magnetic Field Sensor. [Citation Graph (0, 0)][DBLP ] DATE, 1999, pp:239-243 [Conf ] Michel Renovell , Florence Azaïs , Yves Bertrand Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits. [Citation Graph (0, 0)][DBLP ] DATE, 1998, pp:815-821 [Conf ] Yves Bertrand , Marie-Lise Flottes , Florence Azaïs , Serge Bernard , Laurent Latorre , Regis Lorival European Network for Test Education. [Citation Graph (0, 0)][DBLP ] DELTA, 2002, pp:230-234 [Conf ] Marie-Lise Flottes , Yves Bertrand , L. Balado , E. Lupon , Anton Biasizzo , Franc Novak , Stefano Di Carlo , Paolo Prinetto , N. Pricopi , Hans-Joachim Wunderlich Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ. [Citation Graph (0, 0)][DBLP ] DELTA, 2004, pp:135-139 [Conf ] Serge Bernard , Florence Azaïs , Yves Bertrand , Michel Renovell Analog BIST Generator for ADC Testing. [Citation Graph (0, 0)][DBLP ] DFT, 2001, pp:338-346 [Conf ] Yves Bertrand , Guillaume Damiand , Christophe Fiorio Topological Encoding of 3D Segmented Images. [Citation Graph (0, 0)][DBLP ] DGCI, 2000, pp:311-324 [Conf ] Yves Bertrand , Christophe Fiorio , Yann Pennaneach Border Map: A Topological Representation for nD Image Analysis. [Citation Graph (0, 0)][DBLP ] DGCI, 1999, pp:242-257 [Conf ] Michel Renovell , P. Huc , Yves Bertrand The Configuration Ratio: A Model for Simulating CMOS Intra-Gate Bridge with Variable Logic Thresholds. [Citation Graph (0, 0)][DBLP ] EDCC, 1994, pp:165-177 [Conf ] Michel Renovell , P. Huc , Yves Bertrand The Logic Threshold Based Voting: A Model for Local Feedback Bridging Fault. [Citation Graph (0, 0)][DBLP ] EDCC, 1996, pp:205-213 [Conf ] Florence Azaïs , Serge Bernard , Yves Bertrand , Michel Renovell On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2001, pp:425-436 [Conf ] Vincent Beroulle , Yves Bertrand , Laurent Latorre , Pascal Nouet Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2001, pp:461-472 [Conf ] Serge Bernard , Mariane Comte , Florence Azaïs , Yves Bertrand , Michel Renovell A New Methodology For ADC Test Flow Optimization. [Citation Graph (0, 0)][DBLP ] ITC, 2003, pp:201-209 [Conf ] Yves Bertrand , Frédéric Bancel , Michel Renovell Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1993, pp:989-997 [Conf ] Michel Renovell , Yves Bertrand Test Strategy Sensitivity to Defect Parameters. [Citation Graph (0, 0)][DBLP ] ITC, 1997, pp:607-616 [Conf ] Michel Renovell , Jean Marc Galliere , Florence Azaïs , Serge Bernard , Yves Bertrand Boolean and current detection of MOS transistor with gate oxide short. [Citation Graph (0, 0)][DBLP ] ITC, 2001, pp:1039-1048 [Conf ] Michel Renovell , André Ivanov , Yves Bertrand , Florence Azaïs , Sumbal Rafiq Optimal conditions for Boolean and current detection of floating gate faults. [Citation Graph (0, 0)][DBLP ] ITC, 1999, pp:477-486 [Conf ] Yves Bertrand , Florence Azaïs , Marie-Lise Flottes , Regis Lorival A Successful Distance-Learning Experience for IC Test Education. [Citation Graph (0, 0)][DBLP ] MSE, 1999, pp:20-21 [Conf ] Yves Bertrand , Marie-Lise Flottes , L. Balado , Joan Figueras , Anton Biasizzo , Franc Novak , Stefano Di Carlo , Paolo Prinetto , N. Pricopi , Hans-Joachim Wunderlich , J.-P. Van der Heyden Test Engineering Education in Europe: the EuNICE-Test Project. [Citation Graph (0, 0)][DBLP ] MSE, 2003, pp:85-86 [Conf ] Yves Bertrand , Jean-François Dufourd , Jean Françon , Pascal Lienhardt Algebraic Specification and Development in Geometric Modeling. [Citation Graph (0, 0)][DBLP ] TAPSOFT, 1993, pp:75-89 [Conf ] Yves Bertrand , Frédéric Bancel , Michel Renovell A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1993, pp:51-54 [Conf ] Vincent Beroulle , Yves Bertrand , Laurent Latorre , Pascal Nouet Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical Systems. [Citation Graph (0, 0)][DBLP ] VTS, 2002, pp:439-444 [Conf ] Florence Azaïs , Serge Bernard , Yves Bertrand , Xavier Michel , Michel Renovell A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. [Citation Graph (0, 0)][DBLP ] VTS, 2001, pp:266-271 [Conf ] Florence Azaïs , Michel Renovell , Yves Bertrand , J-C. Bodin Design-For-Testability for Switched-Current Circuits. [Citation Graph (0, 0)][DBLP ] VTS, 1998, pp:370-375 [Conf ] Michel Renovell , Florence Azaïs , Yves Bertrand The multi-configuration: A DFT technique for analog circuits. [Citation Graph (0, 0)][DBLP ] VTS, 1996, pp:54-59 [Conf ] Michel Renovell , Florence Azaïs , Serge Bernard , Yves Bertrand Hardware Resource Minimization for Histogram-Based ADC BIST. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:247-254 [Conf ] Michel Renovell , P. Huc , Yves Bertrand The concept of resistance interval: a new parametric model for realistic resistive bridging fault. [Citation Graph (0, 0)][DBLP ] VTS, 1995, pp:184-189 [Conf ] Michel Renovell , P. Huc , Yves Bertrand Bridging fault coverage improvement by power supply control. [Citation Graph (0, 0)][DBLP ] VTS, 1996, pp:338-343 [Conf ] Franck Ledoux , Agnès Arnould , Pascale Le Gall , Yves Bertrand Geometric Modelling with CASL. [Citation Graph (0, 0)][DBLP ] WADT, 2001, pp:176-200 [Conf ] Sylvain Thery , Dominique Bechmann , Yves Bertrand N-Dimensional Gregory-Bezier for N-Dimensional Cellular Complexes. [Citation Graph (0, 0)][DBLP ] WSCG (Short Papers), 2001, pp:16-23 [Conf ] Yves Bertrand , Jean-François Dufourd Algebraic Specification of a 3D-Modeler Based on Hypermaps. [Citation Graph (0, 0)][DBLP ] CVGIP: Graphical Model and Image Processing, 1994, v:56, n:1, pp:29-60 [Journal ] Guillaume Damiand , Yves Bertrand , Christophe Fiorio Topological model for two-dimensional image representation: definition and optimal extraction algorithm. [Citation Graph (0, 0)][DBLP ] Computer Vision and Image Understanding, 2004, v:93, n:2, pp:111-154 [Journal ] Florence Azaïs , Yves Bertrand , Michel Renovell , André Ivanov , Sassan Tabatabaei An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2003, v:20, n:1, pp:60-67 [Journal ] Michel Renovell , Florence Azaïs , Yves Bertrand Improving Defect Detection in Static-Voltage Testing. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2002, v:19, n:6, pp:83-89 [Journal ] Jean Marc Galliere , Michel Renovell , Florence Azaïs , Yves Bertrand Delay Testing Viability of Gate Oxide Short Defects. [Citation Graph (0, 0)][DBLP ] J. Comput. Sci. Technol., 2005, v:20, n:2, pp:195-200 [Journal ] Sylvain Brandel , Dominique Bechmann , Yves Bertrand Thickening: an operation for animation. [Citation Graph (0, 0)][DBLP ] Journal of Visualization and Computer Animation, 2000, v:11, n:5, pp:261-277 [Journal ] André Ivanov , Sumbal Rafiq , Michel Renovell , Florence Azaïs , Yves Bertrand On the detectability of CMOS floating gate transistor faults. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:116-128 [Journal ] Jean Françon , Yves Bertrand Topological 3D-manifolds: a statistical study of the cells. [Citation Graph (0, 0)][DBLP ] Theor. Comput. Sci., 2000, v:234, n:1-2, pp:233-254 [Journal ] Franck Ledoux , Jean-Marc Mota , Agnès Arnould , Catherine Dubois , Pascale Le Gall , Yves Bertrand Spécifications formelles du chanfreinage. [Citation Graph (0, 0)][DBLP ] Technique et Science Informatiques, 2002, v:21, n:8, pp:1073-1098 [Journal ] Sylvain Prat , Patrick Gioia , Yves Bertrand , Daniel Meneveaux Connectivity compression in an arbitrary dimension. [Citation Graph (0, 0)][DBLP ] The Visual Computer, 2005, v:21, n:8-10, pp:876-885 [Journal ] Sebastien Horna , Guillaume Damiand , Daniel Meneveaux , Yves Bertrand Building 3D indoor scenes topology from 2D architectural plans. [Citation Graph (0, 0)][DBLP ] GRAPP (GM/R), 2007, pp:37-44 [Conf ] Florence Azaïs , Serge Bernard , Yves Bertrand , Mariane Comte , Michel Renovell A-to-D converters static error detection from dynamic parameter measurement. [Citation Graph (0, 0)][DBLP ] Microelectronics Journal, 2003, v:34, n:10, pp:945-953 [Journal ] Florence Azaïs , Serge Bernard , Yves Bertrand , Mariane Comte , Michel Renovell Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. [Citation Graph (0, 0)][DBLP ] J. Electronic Testing, 2005, v:21, n:3, pp:291-298 [Journal ] Generic computation of bulletin boards into geometric kernels. [Citation Graph (, )][DBLP ] On-chip analog output response compaction. [Citation Graph (, )][DBLP ] MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits. [Citation Graph (, )][DBLP ] An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. [Citation Graph (, )][DBLP ] On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring. [Citation Graph (, )][DBLP ] Considerations on Improving the Design of CUFF Electrode for ENG Recording - Geometrical Approach, Dedicated IC, Sensitivity, Noise Rejection. [Citation Graph (, )][DBLP ] Multipolar Electrode and Preamplifier Design for ENG-Signal Acquisition. [Citation Graph (, )][DBLP ] Consistency constraints and 3D building reconstruction. [Citation Graph (, )][DBLP ] Search in 0.022secs, Finished in 0.027secs