The SCEAS System
Navigation Menu

Search the dblp DataBase


Andrzej Hlawiczka: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dariusz Badura, Andrzej Hlawiczka
    Low Cost Bist for Edac Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:410-415 [Conf]
  2. Andrzej Hlawiczka, Michal Kopec
    Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:380-385 [Conf]
  3. Tomasz Garbolino, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka
    Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:230-231 [Conf]
  4. Tomasz Rudnicki, Andrzej Hlawiczka
    Test Pattern Generator for Delay Faults. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:255-258 [Conf]
  5. Tomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka
    Avoiding Crosstalk Influence on Interconnect Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:149-152 [Conf]
  6. Tomasz Garbolino, Andrzej Hlawiczka
    A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    EDCC, 1999, pp:321-338 [Conf]
  7. Andrzej Hlawiczka, Jacek Binda
    Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera Structures. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:120-122 [Conf]
  8. Andrzej Hlawiczka, Dariusz Badura
    Universal Test Controller Chip for Board Self Test. [Citation Graph (0, 0)][DBLP]
    Fehlertolerierende Rechensysteme, 1987, pp:165-175 [Conf]
  9. Andrzej Hlawiczka
    Compression of multiple-valued data serial streams by means of parallel LFSR signature analyzer. [Citation Graph (0, 0)][DBLP]
    Fehlertolerierende Rechensysteme, 1984, pp:404-416 [Conf]
  10. Andrzej Hlawiczka
    Signature Analysis Testing with Bottom-Top Exclusive Or Type MISR. [Citation Graph (0, 0)][DBLP]
    Fehlertolerierende Rechensysteme, 1989, pp:356-367 [Conf]
  11. Andrzej Hlawiczka, Michael Gössel, Egor S. Sogomonyan
    A linear code-preserving signature analyzer COPMISR. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:350-355 [Conf]
  12. Andrzej Hlawiczka
    Comments on `` Procedures for Eliminating Static and Dynamic-Hazards in Test Generation''. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:2, pp:191- [Journal]
  13. Andrzej Hlawiczka
    Compression of Three-State Data Serial Streams by Means of a Parallel LFSR Signature Analyzer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:8, pp:732-741 [Journal]
  14. Andrzej Hlawiczka
    Parallel Signature Analyzers Using Hybrid Design of Their Linear Feedbacks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:12, pp:1562-1571 [Journal]
  15. Tomasz Garbolino, Andrzej Hlawiczka
    Efficient test pattern generators based on specific cellular automata structures. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:6, pp:975-983 [Journal]
  16. Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
    Test-per-Clock Detection, Localization and Identification of Interconnect Faults. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:233-238 [Conf]

  17. Interconnect Faults Identification and Localization Using Modified Ring LFSRs. [Citation Graph (, )][DBLP]

  18. Effective BIST for crosstalk faults in interconnects. [Citation Graph (, )][DBLP]

Search in 0.183secs, Finished in 0.184secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002