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Publications of Author

1. Ameet Bagwe, Rubin A. Parekhji
   Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2000, pp:260-0 [Conf]
   
2. Sameer Goel, Rubin A. Parekhji
   Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2005, pp:330-336 [Conf]
   
3. Michael Nicolaidis, Rubin A. Parekhji, M. Boudjit
   E-Groups: A New Technique for Fast Backward Propagation in System Level Test Generation. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1996, pp:34-41 [Conf]
   
4. Rubin A. Parekhji
   DFT for Low Cost SOC Test. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2005, pp:451- [Conf]
   
5. Ambar A. Gadkari, S. Ramesh, Rubin A. Parekhji
   CESC: a visual formalism for specification and verification of SoCs. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2004, pp:354-357 [Conf]
   
6. Jais Abraham, Narayan Prasad, Srinivasa Chakravarthy B. S., Ameet Bagwe, Rubin A. Parekhji
   A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx. [Citation Graph (0, 0)][DBLP]
   ITC, 2000, pp:417-425 [Conf]
   
7. K. Nikila, Rubin A. Parekhji
   DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device. [Citation Graph (0, 0)][DBLP]
   ITC, 2004, pp:773-782 [Conf]
   
8. Rubin A. Parekhji
   Panel Synopsis - How (In)Adequate is One Time Testing?. [Citation Graph (0, 0)][DBLP]
   ITC, 2003, pp:1279- [Conf]
   
9. Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
   A Methodology for Designing Optimal Self-Checking Sequential Circuits. [Citation Graph (0, 0)][DBLP]
   ITC, 1991, pp:283-291 [Conf]
   
10. Rubin A. Parekhji, N. K. Nanda
    Design methodology and microdiagnostics development for a self-checking microprocessor. [Citation Graph (0, 0)][DBLP]
    MICRO, 1989, pp:70-82 [Conf]
    
11. B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh
    A new methodology for the design of low-cost fail safe circuits and networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:355-358 [Conf]
    
12. Rubin A. Parekhji
    Test Techniques and Trade-offs for Embedded Cores and Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:5- [Conf]
    
13. Rubin A. Parekhji
    Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:17- [Conf]
    
14. Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
    State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:15-20 [Conf]
    
15. Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar
    Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:753-756 [Conf]
    
16. Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji
    Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:781-788 [Conf]
    
17. Subir K. Roy, Rubin A. Parekhji
    Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:364-372 [Conf]
    
18. Satish Yada, Bharadwaj Amrutur, Rubin A. Parekhji
    Modified Stability Checking for On-line Error Detection. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:787-792 [Conf]
    
19. Sandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin A. Parekhji
    Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:339-344 [Conf]
    
20. Rubin A. Parekhji
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:86-87 [Conf]
    
21. Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
    Concurrent Error Detection Using Monitoring Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:3, pp:24-32 [Journal]
    
22. Carol Stolicny, Tapio Koivukangas, Rubin A. Parekhji, Ian G. Harris, Rob Aitken
    ITC 2003 panels: Part 1. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:2, pp:160-163 [Journal]
    
23. 
    Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage. [Citation Graph (, )][DBLP]
    
    
24. 
    Methodology for low power test pattern generation using activity threshold control logic. [Citation Graph (, )][DBLP]
    
    
25. 
    False Error Study of On-line Soft Error Detection Mechanisms. [Citation Graph (, )][DBLP]
    
    
26. 
    Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test. [Citation Graph (, )][DBLP]
    
    
27. 
    A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips. [Citation Graph (, )][DBLP]
    
    
28. 
    A systematic approach to synthesis of verification test-suites for modular SoC designs. [Citation Graph (, )][DBLP]