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Pierluigi Civera:
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- Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
FPGA-Based Fault Injection for Microprocessor Systems. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2001, pp:304-0 [Conf]
- Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . [Citation Graph (0, 0)][DBLP] DFT, 2001, pp:250-258 [Conf]
- Pierluigi Civera, Luca Macchiarulo, Massimo Violante
A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis. [Citation Graph (0, 0)][DBLP] DFT, 2002, pp:31-39 [Conf]
- Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda, Pierluigi Civera
An Integrated HW and SW Fault Injection Environment for Real-Time Systems. [Citation Graph (0, 0)][DBLP] DFT, 1998, pp:117-0 [Conf]
- Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. [Citation Graph (0, 0)][DBLP] FPL, 2001, pp:493-502 [Conf]
- Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
Exploiting FPGA for Accelerating Fault Injection Experiments. [Citation Graph (0, 0)][DBLP] IOLTW, 2001, pp:9-13 [Conf]
- Pierluigi Civera, F. Maddaleno, Gianluca Piccinini, Maurizio Zamboni
An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results. [Citation Graph (0, 0)][DBLP] ISCA, 1987, pp:117-126 [Conf]
- Luca Macchiarulo, Pierluigi Civera
Ternary Decision Diagrams with Inverted Edges and Cofactoring - An Application to Discrete Neural Networks Synthesis. [Citation Graph (0, 0)][DBLP] ISMVL, 1998, pp:58-0 [Conf]
- Crina Anton, Pierluigi Civera, Ionel Colonescu, Enrico Macii, Massimo Poncino, Alessandro Bogliolo
RTL Estimation of Steering Logic Power. [Citation Graph (0, 0)][DBLP] PATMOS, 2000, pp:36-46 [Conf]
- Luca Macchiarulo, Pierluigi Civera
Functional Decomposition through Structural Analysis of Decision Diagrams - the Binary and Multiple-Valued Cases. [Citation Graph (0, 0)][DBLP] VLSI Design, 1999, pp:218-0 [Conf]
- Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
New techniques for efficiently assessing reliability of SOCs. [Citation Graph (0, 0)][DBLP] Microelectronics Journal, 2003, v:34, n:1, pp:53-61 [Journal]
Wireless Sensor Networks for Intelligent Transportation Systems. [Citation Graph (, )][DBLP]
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