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Luca Macchiarulo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    FPGA-Based Fault Injection for Microprocessor Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:304-0 [Conf]
  2. Y. Bellan, Mario Costa, Giancarlo Ferrigno, Fabrizio Lombardi, Luca Macchiarulo, Alfonso Montuori, Eros Pasero, Camilla Rigotti
    Artificial Neural Networks for Motion Emulation in Virtual Environments. [Citation Graph (0, 0)][DBLP]
    CAPTECH, 1998, pp:83-99 [Conf]
  3. Luca Benini, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino
    From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:784-789 [Conf]
  4. Mario R. Casu, Luca Macchiarulo
    A new approach to latency insensitive design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:576-581 [Conf]
  5. Luca Macchiarulo, Malgorzata Marek-Sadowska
    Wave-steering one-hot encoded FSMs. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:357-360 [Conf]
  6. Mario R. Casu, Luca Macchiarulo
    Issues in Implementing Latency Insensitive Protocols. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1390-1391 [Conf]
  7. Mario R. Casu, Luca Macchiarulo
    A New System Design Methodology for Wire Pipelined SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:944-945 [Conf]
  8. Luca Macchiarulo, Luca Benini, Enrico Macii
    On-the-fly layout generation for PTL macrocells. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:546-551 [Conf]
  9. Luca Macchiarulo, Enrico Macii, Massimo Poncino
    Wire Placement for Crosstalk Energy Minimization in Address Buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:158-162 [Conf]
  10. Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska
    Wave Steered FSMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:270-276 [Conf]
  11. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:250-258 [Conf]
  12. Pierluigi Civera, Luca Macchiarulo, Massimo Violante
    A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:31-39 [Conf]
  13. Amit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska
    A novel high throughput reconfigurable FPGA architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:22-29 [Conf]
  14. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:493-502 [Conf]
  15. Monica Donno, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino
    Enhanced clustered voltage scaling for low power. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:18-23 [Conf]
  16. Luca Macchiarulo, Consolato F. Caccamo, Davide Pandini
    A comparison between mask- and field-programmable routing structures on industrial FPGA architectures. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:436-439 [Conf]
  17. Sergio Tota, Mario R. Casu, Luca Macchiarulo
    Implementation analysis of NoC: a MPSoC trace-driven approach. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:204-209 [Conf]
  18. Mario R. Casu, Luca Macchiarulo
    On-Chip Transparent Wire Pipelining. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:160-167 [Conf]
  19. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Exploiting FPGA for Accelerating Fault Injection Experiments. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:9-13 [Conf]
  20. Luca Macchiarulo, Enrico Macii, Massimo Poncino
    Low-energy for deep-submicron address buses. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:176-181 [Conf]
  21. Luca Macchiarulo, Pierluigi Civera
    Ternary Decision Diagrams with Inverted Edges and Cofactoring - An Application to Discrete Neural Networks Synthesis. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:58-0 [Conf]
  22. Mario R. Casu, Luca Macchiarulo
    Floorplanning for throughput. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:62-69 [Conf]
  23. Mario R. Casu, Luca Macchiarulo
    Floorplan assisted data rate enhancement through wire pipelining: a real assessment. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:121-128 [Conf]
  24. Luca Macchiarulo, Pierluigi Civera
    Functional Decomposition through Structural Analysis of Decision Diagrams - the Binary and Multiple-Valued Cases. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:218-0 [Conf]
  25. Elena Dubrova, Luca Macchiarulo
    A Comment on 'Graph-Based Algorithm for Boolean Function Manipulation'. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:11, pp:1290-1292 [Journal]
  26. Luca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska
    Pipelining Sequential Circuits with Wave Steering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:9, pp:1205-1210 [Journal]
  27. Mario R. Casu, Luca Macchiarulo
    Throughput-driven floorplanning with wire pipelining. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:5, pp:663-675 [Journal]
  28. Luca Benini, Luca Macchiarulo, Alberto Macii, Massimo Poncino
    Layout-driven memory synthesis for embedded systems-on-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:96-105 [Journal]
  29. Amit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska
    PITIA: an FPGA for throughput-intensive applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:354-363 [Journal]
  30. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    New techniques for efficiently assessing reliability of SOCs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:1, pp:53-61 [Journal]

  31. Enhancing double-patterning detailed routing with lazy coloring and within-path conflict avoidance. [Citation Graph (, )][DBLP]


  32. Adaptive Latency-Insensitive Protocols. [Citation Graph (, )][DBLP]


  33. Adaptive Latency Insensitive Protocols and Elastic Circuits with Early Evaluation: A Comparative Analysis. [Citation Graph (, )][DBLP]


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