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Title:
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Massimo Violante: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    FPGA-Based Fault Injection for Microprocessor Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:304-0 [Conf]
  2. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:68-73 [Conf]
  3. Marcello Lajolo, Luciano Lavagno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Automatic test bench generation for simulation-based validation. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:136-140 [Conf]
  4. M. Bellato, Paolo Bernardi, D. Bortolato, A. Candelori, M. Ceschia, A. Paccagnella, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, P. Zambolin
    Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:584-589 [Conf]
  5. Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10720-10725 [Conf]
  6. Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante
    Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:670-0 [Conf]
  7. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
    On the test of microprocessor IP cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:209-213 [Conf]
  8. Ph. Cheynet, B. Nicolescu, Raoul Velazco, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    System safety through automatic high-level code transformations: an experimental evaluation. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:297-301 [Conf]
  9. O. Goloubeva, Matteo Sonza Reorda, Massimo Violante
    Automatic Generation of Validation Stimuli for Application-Specific Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:188-193 [Conf]
  10. Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno
    Evaluating System Dependability in a Co-Design Framework. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:586-590 [Conf]
  11. Maurizio Martina, Guido Masera, Andrea Molino, Fabrizio Vacca, Luca Sterpone, Massimo Violante
    A new approach to compress the configuration information of programmable devices. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:48-51 [Conf]
  12. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10602-10607 [Conf]
  13. Luca Sterpone, Massimo Violante
    ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:54-58 [Conf]
  14. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:250-258 [Conf]
  15. Pierluigi Civera, Luca Macchiarulo, Massimo Violante
    A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:31-39 [Conf]
  16. Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante
    Optimal Vector Selection for Low Power BIST. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:219-226 [Conf]
  17. Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante
    Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:336-343 [Conf]
  18. Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:445-453 [Conf]
  19. O. Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Soft-Error Detection Using Control Flow Assertions. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:581-588 [Conf]
  20. J. Pérez, Matteo Sonza Reorda, Massimo Violante
    Dependability Analysis of CAN Networks: An Emulation-Based Approach. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:537-0 [Conf]
  21. Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante
    An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:257-265 [Conf]
  22. Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante
    Soft-Error Detection through Software Fault-Tolerance Techniques. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:210-218 [Conf]
  23. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    A New Functional Fault Model for FPGA Application-Oriented Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:372-380 [Conf]
  24. Matteo Sonza Reorda, Massimo Violante
    Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:263-274 [Conf]
  25. Matteo Sonza Reorda, Massimo Violante
    On-Line Analysis and Perturbation of CAN Networks. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:424-432 [Conf]
  26. Luca Sterpone, Massimo Violante
    A design flow for protecting FPGA-based systems against single event upsets. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:436-444 [Conf]
  27. Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante
    Online hardening of programs against SEUs and SETs. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:280-290 [Conf]
  28. Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto
    Combined software and hardware techniques for the design of reliable IP processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:265-273 [Conf]
  29. Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
    On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core. [Citation Graph (0, 0)][DBLP]
    DSN, 2005, pp:50-58 [Conf]
  30. Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Prediction of Power Requirements for High-Speed Circuits. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2000, pp:247-254 [Conf]
  31. Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Test Pattern Generation Under Low Power Constraints. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 1999, pp:162-170 [Conf]
  32. Ernesto Sánchez, Giovanni Squillero, Massimo Violante
    Exploiting HW Acceleration for Classifying Complex Test Program Generation Problems. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2004, pp:230-239 [Conf]
  33. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:493-502 [Conf]
  34. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:607-615 [Conf]
  35. Matteo Sonza Reorda, Massimo Violante
    Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:616-626 [Conf]
  36. Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero, Luca Sterpone, Massimo Violante
    New evolutionary techniques for test-program generation for complex microprocessor cores. [Citation Graph (0, 0)][DBLP]
    GECCO, 2005, pp:2193-2194 [Conf]
  37. Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    ALPS: A Peak Power Estimation Tool for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:350-353 [Conf]
  38. Luca Sterpone, Massimo Violante
    A new hardware architecture for performing the gridding of DNA microarray images. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:341-346 [Conf]
  39. Luca Sterpone, Massimo Violante
    A new decompression system for the configuration process of SRAM-based FPGAS. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:241-246 [Conf]
  40. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
    A genetic algorithm-based system for generating test programs for microprocessor IP cores. [Citation Graph (0, 0)][DBLP]
    ICTAI, 2000, pp:195-198 [Conf]
  41. Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante
    On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:115-120 [Conf]
  42. Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
    Hybrid Soft Error Detection by Means of Infrastructure IP Cores. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:79-88 [Conf]
  43. O. Goloubeva, Matteo Sonza Reorda, Massimo Violante
    An RT-level Concurrent Error Detection Technique for Data Dominated Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:159- [Conf]
  44. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Exploiting FPGA for Accelerating Fault Injection Experiments. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:9-13 [Conf]
  45. B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    New Techniques for Accelerating Fault Injection in VHDL Descriptions. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:61-66 [Conf]
  46. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Analysis of SEU Effects in a Pipelined Processor. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:112-116 [Conf]
  47. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Ph. Cheynet, B. Nicolescu, Raoul Velazco
    Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:17-0 [Conf]
  48. Matteo Sonza Reorda, Massimo Violante
    Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:101-105 [Conf]
  49. Matteo Sonza Reorda, Luca Sterpone, Massimo Violante
    Efficient Estimation of SEU Effects in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:54-59 [Conf]
  50. Massimo Violante, M. Ceschia, Matteo Sonza Reorda, A. Paccagnella, Paolo Bernardi, Maurizio Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori
    Analyzing SEU Effects in SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:119-123 [Conf]
  51. Luca Sterpone, Massimo Violante
    Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:189-190 [Conf]
  52. Matteo Sonza Reorda, Massimo Violante
    Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:229-234 [Conf]
  53. Davide Appello, Paolo Bernardi, Alessandra Fudoli, Maurizio Rebaudengo, Matteo Sonza Reorda, Vincenzo Tancorre, Massimo Violante
    Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:379-385 [Conf]
  54. Paolo Bernardi, Leticia Maria Veiras Bolzani, Alberto Manzone, Marcella Guagliumi Massimo Osella, Massimo Violante, Matteo Sonza Reorda
    Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:3-8 [Conf]
  55. Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reorda, Massimo Violante
    Early Power Estimation for System-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:108-117 [Conf]
  56. B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Speeding-Up Fault Injection Campaigns in VHDL Models. [Citation Graph (0, 0)][DBLP]
    SAFECOMP, 2000, pp:27-36 [Conf]
  57. Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
    Automatic generation of test sets for SBST of microprocessor IP cores. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:74-79 [Conf]
  58. Fulvio Corno, Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante
    A multi-level approach to the dependability analysis of networked systems based on the CAN protocol. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:71-75 [Conf]
  59. J. Pérez, Matteo Sonza Reorda, Massimo Violante
    Accurate Dependability Analysis of CAN-Based Networked Systems. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:337-342 [Conf]
  60. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Marco Torchiano
    A Source-to-Source Compiler for Generating Dependable Software. [Citation Graph (0, 0)][DBLP]
    SCAM, 2001, pp:35-44 [Conf]
  61. Marcello Lajolo, Matteo Sonza Reorda, Massimo Violante
    Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:371-0 [Conf]
  62. Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
    Low Power BIST via Non-Linear Hybrid Cellular Automata. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:29-34 [Conf]
  63. Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante
    Early, Accurate Dependability Analysis of CAN-Based Networked Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:1, pp:38-45 [Journal]
  64. Matteo Sonza Reorda, Massimo Violante
    Efficient analysis of single event transients. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:5, pp:239-246 [Journal]
  65. Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
    A New Hybrid Fault Detection Technique for Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:185-198 [Journal]
  66. Luca Sterpone, Massimo Violante
    A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:6, pp:732-744 [Journal]
  67. Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante
    SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:191-202 [Journal]
  68. Salvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante
    Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:194-196 [Conf]
  69. Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena
    Fault Injection-based Reliability Evaluation of SoPCs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:75-82 [Conf]
  70. Luca Sterpone, Massimo Violante
    Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:159-164 [Conf]
  71. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    New techniques for efficiently assessing reliability of SOCs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:1, pp:53-61 [Journal]
  72. Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro
    Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:1, pp:47-54 [Journal]

  73. A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs. [Citation Graph (, )][DBLP]


  74. A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips. [Citation Graph (, )][DBLP]


  75. Optimization of Self Checking FIR filters by means of Fault Injection Analysis. [Citation Graph (, )][DBLP]


  76. Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs. [Citation Graph (, )][DBLP]


  77. An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs. [Citation Graph (, )][DBLP]


  78. Coping with Obsolescence of Processor Cores in Critical Applications. [Citation Graph (, )][DBLP]


  79. Soft errors in Flash-based FPGAs: Analysis methodologies and first results. [Citation Graph (, )][DBLP]


  80. On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs. [Citation Graph (, )][DBLP]


  81. A low-cost solution for developing reliable Linux-based space computers for on-board data handling. [Citation Graph (, )][DBLP]


  82. Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs. [Citation Graph (, )][DBLP]


  83. An integrated flow for the design of hardened circuits on SRAM-based FPGAs. [Citation Graph (, )][DBLP]


  84. An in-vehicle infotainment software architecture based on google android. [Citation Graph (, )][DBLP]


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