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Dong Hyun Baik: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dong Hyun Baik, Kewal K. Saluja
    State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:272-277 [Conf]
  2. Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
    A yield improvement methodology using pre- and post-silicon statistical clock scheduling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:611-618 [Conf]
  3. Dong Hyun Baik, Kewal K. Saluja
    Test Cost Reduction Using Partitioned Grid Random Access Scan. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:169-174 [Conf]
  4. Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara
    Random Access Scan: A solution to test power, test data volume and test time. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:883-888 [Conf]
  5. Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja
    Exclusive Test and its Applications to Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:143-148 [Conf]
  6. Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
    False Path and Clock Scheduling Based Yield-Aware Gate Sizing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:423-426 [Conf]
  7. Kim T. Le, Dong Hyun Baik, Kewal K. Saluja
    Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:769-774 [Conf]
  8. Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
    Yield-Driven, False-Path-Aware Clock Skew Scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:3, pp:214-222 [Journal]

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