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Tapan J. Chakraborty: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tapan J. Chakraborty
    Efficient Test Architecture based on Boundary Scan for Comprehensive System Test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:464-465 [Conf]
  2. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
    Delay Fault Models and Test Generation for Random Logic Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:165-172 [Conf]
  3. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
    Design for Testability for Path Delay faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:453-457 [Conf]
  4. Tapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin
    Enhanced Controllability for IDDQ Test Sets Using Partial Scan. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:278-281 [Conf]
  5. Roystein Oliveira, Aditya Jagirdar, Tapan J. Chakraborty
    A TMR Scheme for SEU Mitigation in Scan Flip-Flops. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:905-910 [Conf]
  6. Vishwani D. Agrawal, Tapan J. Chakraborty
    High-Performance Circuit Testing with Slow-Speed Testers. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:302-310 [Conf]
  7. Tapan J. Chakraborty, Vishwani D. Agrawal
    Effective Path Selection for Delay Fault Testing of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:998-1003 [Conf]
  8. Tapan J. Chakraborty, Chen-Huan Chiang
    A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:923-929 [Conf]
  9. Tapan J. Chakraborty, Sumit Ghosh
    On Behavior Fault Modeling for Combinational Digital Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:593-600 [Conf]
  10. Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik
    A BIST scheme for the detection of path-delay faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:422-0 [Conf]
  11. Tapan J. Chakraborty, Vishwani D. Agrawal
    Robust testing for stuck-at faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:42-46 [Conf]
  12. Tapan J. Chakraborty, Vishwani D. Agrawal
    Design for high-speed testability of stuck-at faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:53-56 [Conf]
  13. Tapan J. Chakraborty, Vishwani D. Agrawal
    Simulation of at-speed tests for stuck-at faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:216-220 [Conf]
  14. Wu-Tung Cheng, Tapan J. Chakraborty
    Gentest: An Automatic Test-Generation System for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1989, v:22, n:4, pp:43-49 [Journal]
  15. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
    On variable clock methods for path delay testing of sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1237-1249 [Journal]
  16. Brendan Mullane, Chen-Huan Chiang, Michael Higgins, Ciaran MacNamee, Tapan J. Chakraborty, Thomas B. Cook
    FPGA Prototyping of a Scan Based System-On-Chip Design. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:121-126 [Conf]
  17. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
    Improving path delay testability of sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:736-741 [Journal]
  18. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
    Path delay fault simulation of sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:223-228 [Journal]

  19. A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits. [Citation Graph (, )][DBLP]


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