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Nur A. Touba: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil
    Compressing Functional Tests for Microprocessors. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:428-433 [Conf]
  2. Abhijit Jas, Kartik Mohanram, Nur A. Touba
    An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:275-0 [Conf]
  3. Madhavi Karkala, Nur A. Touba, Hans-Joachim Wunderlich
    Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:492-499 [Conf]
  4. Eric MacDonald, Nur A. Touba
    Testing domino circuits in SOI technology. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:441-446 [Conf]
  5. Kedarnath J. Balakrishnan, Nur A. Touba
    Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1130-1135 [Conf]
  6. Ranganathan Sankaralingam, Nur A. Touba
    Reducing Test Power During Test Using Programmable Scan Chain Disable. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:159-166 [Conf]
  7. Kedarnath J. Balakrishnan, Nur A. Touba
    Matrix-Based Test Vector Decompression Using an Embedded Processor. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:159-165 [Conf]
  8. Kedarnath J. Balakrishnan, Nur A. Touba
    Scan-Based BIST Diagnosis Using an Embedded Processor. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:209-216 [Conf]
  9. Jayabrata Ghosh-Dastidar, Nur A. Touba
    Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:215-220 [Conf]
  10. Jayabrata Ghosh-Dastidar, Nur A. Touba
    A Systematic Approach for Diagnosing Multiple Delay Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:211-216 [Conf]
  11. C. V. Krishna, Nur A. Touba
    Hybrid BIST Using an Incrementally Guided LFSR. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:217-224 [Conf]
  12. Jinkyu Lee, Nur A. Touba
    Low Power BIST Based on Scan Partitioning. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:33-41 [Conf]
  13. Kartik Mohanram, Nur A. Touba
    Input Ordering in Concurrent Checkers to Reduce Power Consumption. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:87-98 [Conf]
  14. Kartik Mohanram, Nur A. Touba
    Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:433-0 [Conf]
  15. Ranganathan Sankaralingam, Nur A. Touba
    Inserting Test Points to Control Peak Power During Scan Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:138-146 [Conf]
  16. Samuel I. Ward, Chris Schattauer, Nur A. Touba
    Using Statistical Transformations to Improve Compression for Linear Decompressors. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:42-50 [Conf]
  17. Avijit Dutta, Nur A. Touba
    Synthesis of Efficient Linear Test Pattern Generators. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:206-214 [Conf]
  18. Shalini Ghosh, Eric MacDonald, Sugato Basu, Nur A. Touba
    Low-power weighted pseudo-random BIST using special scan cells. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:86-91 [Conf]
  19. C. V. Krishna, Nur A. Touba
    Adjustable Width Linear Combinational Scan Vector Decompression. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:863-866 [Conf]
  20. Nur A. Touba, Edward J. McCluskey
    Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:651-654 [Conf]
  21. Abhijit Jas, Nur A. Touba
    Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:418-0 [Conf]
  22. Jinkyu Lee, Nur A. Touba
    Low Power Test Data Compression Based on LFSR Reseeding. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:180-185 [Conf]
  23. Nur A. Touba, Edward J. McCluskey
    Pseudo-Random Pattern Testing of Bridging Faults. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:54-60 [Conf]
  24. Debaleena Das, Nur A. Touba, Markus Seuring, Michael Gössel
    Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:171-0 [Conf]
  25. Kartik Mohanram, Egor S. Sogomonyan, Michael Gössel, Nur A. Touba
    Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:35-0 [Conf]
  26. W. Quddus, Abhijit Jas, Nur A. Touba
    Configuration self-test in FPGA-based reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:97-100 [Conf]
  27. P. K. Jaini, Nur A. Touba
    Observing test response of embedded cores through surrounding logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:119-123 [Conf]
  28. Kartik Mohanram, C. V. Krishna, Nur A. Touba
    A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:577-580 [Conf]
  29. Avijit Dutta, Terence Rodrigues, Nur A. Touba
    Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:200-205 [Conf]
  30. Shalini Ghosh, Sugato Basu, Nur A. Touba
    Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:246-249 [Conf]
  31. Kedarnath J. Balakrishnan, Nur A. Touba
    Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:936-944 [Conf]
  32. Debaleena Das, Nur A. Touba
    Reducing test data volume using external/LBIST hybrid test patterns. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:115-122 [Conf]
  33. Jayabrata Ghosh-Dastidar, Debaleena Das, Nur A. Touba
    Fault diagnosis in scan-based BIST using both time and space information. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:95-102 [Conf]
  34. Shalini Ghosh, Nur A. Touba, Sugato Basu
    Reducing Power Consumption in Memory ECC Checkers. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1322-1331 [Conf]
  35. Abhijit Jas, Nur A. Touba
    Test vector decompression via cyclical scan chains and its application to testing core-based designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:458-464 [Conf]
  36. C. V. Krishna, Abhijit Jas, Nur A. Touba
    Test vector encoding using partial LFSR reseeding. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:885-893 [Conf]
  37. C. V. Krishna, Nur A. Touba
    Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:321-330 [Conf]
  38. Eric MacDonald, Nur A. Touba
    Delay testing of SOI circuits: Challenges with the history effect. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:269-275 [Conf]
  39. Kartik Mohanram, Nur A. Touba
    Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:893-901 [Conf]
  40. Bahram Pouya, Nur A. Touba
    Modifying User-Defined Logic for Test Access to Embedded Cores. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:60-68 [Conf]
  41. Nur A. Touba, Edward J. McCluskey
    Automated Logic Synthesis of Random-Pattern-Testable Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:174-183 [Conf]
  42. Nur A. Touba, Edward J. McCluskey
    Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:674-682 [Conf]
  43. Nur A. Touba, Edward J. McCluskey
    Altering a Pseudo-Random Bit Sequence for Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:167-175 [Conf]
  44. Zhe Zhao, Bahram Pouya, Nur A. Touba
    BETSY: synthesizing circuits for a specified BIST environment. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:144-153 [Conf]
  45. Debaleena Das, Nur A. Touba
    A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:266-269 [Conf]
  46. Kedarnath J. Balakrishnan, Nur A. Touba
    Deterministic Test Vector Decompression in Software Using Linear Operations. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:225-231 [Conf]
  47. Avijit Dutta, Nur A. Touba
    Iterative OPDD Based Signal Probability Calculation. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:72-77 [Conf]
  48. Jayabrata Ghosh-Dastidar, Nur A. Touba
    Adaptive Techniques for Improving Delay Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:168-172 [Conf]
  49. Jayabrata Ghosh-Dastidar, Nur A. Touba
    A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:79-88 [Conf]
  50. Shalini Ghosh, Sugato Basu, Nur A. Touba
    Synthesis of Low Power CED Circuits Based on Parity Codes. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:315-320 [Conf]
  51. Debaleena Das, Nur A. Touba
    Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:309-317 [Conf]
  52. Debaleena Das, Nur A. Touba
    Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:370-377 [Conf]
  53. C. V. Krishna, Nur A. Touba
    3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:79-86 [Conf]
  54. Abhijit Jas, Jayabrata Ghosh-Dastidar, Nur A. Touba
    Scan Vector Compression/Decompression Using Statistical Coding. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:114-120 [Conf]
  55. Abhijit Jas, C. V. Krishna, Nur A. Touba
    Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:2-8 [Conf]
  56. Abhijit Jas, Bahram Pouya, Nur A. Touba
    Virtual Scan Chains: A Means for Reducing Scan Length in Cores. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:73-78 [Conf]
  57. Jinkyu Lee, Nur A. Touba
    Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:252-257 [Conf]
  58. Eric MacDonald, Nur A. Touba
    Very Low Voltage Testing of SOI Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:25-30 [Conf]
  59. Kartik Mohanram, Nur A. Touba
    Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:121-127 [Conf]
  60. Bahram Pouya, Nur A. Touba
    Synthesis of Zero-Aliasing Elementary-Tree Space Compactors. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:70-77 [Conf]
  61. Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba
    Static Compaction Techniques to Control Scan Vector Power Dissipation. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:35-42 [Conf]
  62. Ranganathan Sankaralingam, Nur A. Touba
    Controlling Peak Power During Scan Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:153-159 [Conf]
  63. Ranganathan Sankaralingam, Nur A. Touba, Bahram Pouya
    Reducing Power Dissipation during Test Using Scan Chain Disable. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:319-325 [Conf]
  64. Nur A. Touba
    Obtaining High Fault Coverage with Circular BIST Via State Skipping. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:410-415 [Conf]
  65. Nur A. Touba, Edward J. McCluskey
    Transformed pseudo-random patterns for BIST. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:410-416 [Conf]
  66. Nur A. Touba, Edward J. McCluskey
    Test point insertion based on path tracing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:2-8 [Conf]
  67. Nur A. Touba, Edward J. McCluskey
    Applying two-pattern tests using scan-mapping. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:393-399 [Conf]
  68. Nur A. Touba, Bahram Pouya
    Testing Embedded Cores Using Partial Isolation Rings. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:10-16 [Conf]
  69. Avijit Dutta, Nur A. Touba
    Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:349-354 [Conf]
  70. Richard Putman, Nur A. Touba
    Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:211-218 [Conf]
  71. Nur A. Touba
    Survey of Test Vector Compression Techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:4, pp:294-303 [Journal]
  72. Nur A. Touba, Bahram Pouya
    Using Partial Isolation Rings to Test Core-Based Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:4, pp:52-59 [Journal]
  73. Kedarnath J. Balakrishnan, Nur A. Touba
    Matrix-based software test data decompression for systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:5, pp:247-256 [Journal]
  74. Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba
    An efficient test vector compression scheme using selective Huffman coding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:797-806 [Journal]
  75. Nur A. Touba, Edward J. McCluskey
    Bit-fixing in pseudorandom sequences for scan BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:545-555 [Journal]
  76. Nur A. Touba, Edward J. McCluskey
    Logic synthesis of multilevel circuits with concurrent error detection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:783-789 [Journal]
  77. Nur A. Touba, Edward J. McCluskey
    RP-SYN: synthesis of random pattern testable circuits with test point insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:8, pp:1202-1213 [Journal]
  78. C. V. Krishna, Abhijit Jas, Nur A. Touba
    Achieving high encoding efficiency with partial dynamic LFSR reseeding. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:4, pp:500-516 [Journal]
  79. Lei Li, Krishnendu Chakrabarty, Nur A. Touba
    Test data compression using dictionaries with selective entries and fixed-length indices. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:470-490 [Journal]
  80. Abhijit Jas, C. V. Krishna, Nur A. Touba
    Weighted pseudorandom hybrid BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1277-1283 [Journal]
  81. Abhijit Jas, Bahram Pouya, Nur A. Touba
    Test data compression technique for embedded cores using virtual scan chains. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:775-781 [Journal]
  82. Kartik Mohanram, Nur A. Touba
    Lowering power consumption in concurrent checkers via input ordering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:11, pp:1234-1243 [Journal]
  83. Eric MacDonald, Nur A. Touba
    Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:587-595 [Journal]
  84. Kedarnath J. Balakrishnan, Nur A. Touba
    Improving Linear Test Data Compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1227-1237 [Journal]
  85. Nur A. Touba
    Circular BIST with state skipping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:668-672 [Journal]
  86. Shalini Ghosh, Sugato Basu, Nur A. Touba
    Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:1, pp:63-72 [Journal]

  87. Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code. [Citation Graph (, )][DBLP]


  88. Enhancing Silicon Debug via Periodic Monitoring. [Citation Graph (, )][DBLP]


  89. Improving Memory Repair by Selective Row Partitioning. [Citation Graph (, )][DBLP]


  90. Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points. [Citation Graph (, )][DBLP]


  91. Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture. [Citation Graph (, )][DBLP]


  92. Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation. [Citation Graph (, )][DBLP]


  93. Guest Editors' Introduction: Progress in Test Compression. [Citation Graph (, )][DBLP]


  94. ITC 2008 Highlights. [Citation Graph (, )][DBLP]


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