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Sreejit Chakravarty: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sreejit Chakravarty
    Improving Logic Test Quality of Microprocessors. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:- [Conf]
  2. Sreejit Chakravarty
    On the capability of delay tests to detect bridges and opens. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:314-319 [Conf]
  3. Vinay Dabholkar, Sreejit Chakravarty
    Computing stress tests for interconnect defects. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:143-148 [Conf]
  4. Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty
    Untestable Multi-Cycle Path Delay Faults in Industrial Designs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:194-201 [Conf]
  5. Sreejit Chakravarty
    On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:736-739 [Conf]
  6. Sreejit Chakravarty, Yiming Gong
    An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:520-524 [Conf]
  7. Sreejit Chakravarty, Minshen Liu
    Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:353-356 [Conf]
  8. Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel
    Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:133-138 [Conf]
  9. Sujit T. Zachariah, Sreejit Chakravarty, Carl D. Roth
    A novel algorithm to extract two-node bridges. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:790-793 [Conf]
  10. M. M. Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi
    Implicit and Exact Path Delay Fault Grading in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:990-995 [Conf]
  11. Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty
    An Approach to Minimizing Functional Constraints. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:215-226 [Conf]
  12. Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel
    Fault Simulation ofIDDQ Tests for Bridging Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:340-349 [Conf]
  13. Yiming Gong, Sreejit Chakravarty
    On adaptive diagnostic test generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:181-184 [Conf]
  14. Sreenivas Mandava, Sreejit Chakravarty, Sandip Kundu
    On Detecting Bridges Causing Timing Failures. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:400-406 [Conf]
  15. Sreejit Chakravarty, Shambhu J. Upadhyaya
    A Unified Approach to Designing Fault-Tolerant Processor Ensembles. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:339-342 [Conf]
  16. Ajay Shekhawat, Sreejit Chakravarty
    Heuristics for the MSC Problem for Serial and Shared-Memory Computers. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1990, pp:64-67 [Conf]
  17. Sreejit Chakravarty
    Supplemental Test Methods (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:7- [Conf]
  18. Sreejit Chakravarty
    A Testable Realization of CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:509-518 [Conf]
  19. Sreejit Chakravarty, Harry B. Hunt III
    On the Computation of Detection Probability for Multiple Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:252-262 [Conf]
  20. Sreejit Chakravarty, Ankur Jain, Nandakumar Radhakrishnan, Eric W. Savage, Sujit T. Zachariah
    Experimental Evaluation of Scan Tests for Bridges. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:509-518 [Conf]
  21. Sreejit Chakravarty, Eric W. Savage, Eric N. Tran
    Defect Coverage Analysis of Partitioned Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:907-915 [Conf]
  22. Sreejit Chakravarty, Paul J. Thadikaran
    A Study of IDDQ Subset Selection Algorithms for Bridging Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:403-412 [Conf]
  23. Seonki Kim, Sreejit Chakravarty, Bapiraju Vinnakota
    An analysis of the delay defect detection capability of the ECR test method. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1060-1069 [Conf]
  24. Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran
    Techniques to Reduce Data Volume and Application Time for Transition Test. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:983-992 [Conf]
  25. Manan Syal, Michael S. Hsiao, Sreejit Chakravarty
    Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1034-1043 [Conf]
  26. Sujit T. Zachariah, Sreejit Chakravarty
    A scalable and efficient methodology to extract two node bridges from large industrial circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:750-759 [Conf]
  27. Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty
    A new framework for generating optimal March tests for memory arrays. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:73-0 [Conf]
  28. Sreejit Chakravarty, Yiming Gong
    Voting model based diagnosis of bridging faults in combinational circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:338-342 [Conf]
  29. Sreejit Chakravarty, Sivaprakasam Suresh
    IDDQ Measurement Based Diagnosis of Bridging Faults in Full Scan Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:179-182 [Conf]
  30. Vinay Dabholkar, Sreejit Chakravarty
    Computing Stress Tests for Gate Oxide Shorts. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:378-391 [Conf]
  31. Paul J. Thadikaran, Sreejit Chakravarty
    Fast Algorithms for Computer IDDQ Tests for Combination Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:103-106 [Conf]
  32. Sujit T. Zachariah, Sreejit Chakravarty
    A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:333-338 [Conf]
  33. Sujit T. Zachariah, Sreejit Chakravarty
    A Comparative Study of Pseudo Stuck-At and Leakage Fault Model. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:91-94 [Conf]
  34. Yi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee
    Transition Tests for High Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:29-34 [Conf]
  35. Sreejit Chakravarty
    A sampling technique for diagnostic fault simulation. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:192-197 [Conf]
  36. Sreejit Chakravarty, Yi-Shing Chang, Hiep Hoang, Sridhar Jayaraman, Silvio Picano, Cheryl Prunty, Eric W. Savage, Rehan Sheikh, Eric N. Tran, Khen Wee
    Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:337-342 [Conf]
  37. Sreejit Chakravarty, Vinodh Gopal
    Techniques to Encode and Compress Fault Dictionaries. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:195-200 [Conf]
  38. Sreejit Chakravarty, Ankur Jain
    Fault Models for Speed Failures Caused by Bridges and Opens. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:373-378 [Conf]
  39. Sreejit Chakravarty, Kambiz Komeyli, Eric W. Savage, Michael J. Carruthers, Bret T. Stastny, Sujit T. Zachariah
    Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:367-372 [Conf]
  40. Yiming Gong, Sreejit Chakravarty
    Using fault sampling to compute I/sub DDQ/ diagnostic test set. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:74-79 [Conf]
  41. Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel
    Cyclic stress tests for full scan circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:89-94 [Conf]
  42. Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty
    Path Delay Fault Simulation on Large Industrial Designs. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:16-23 [Conf]
  43. Manan Syal, Michael S. Hsiao, Kiran B. Doreswamy, Sreejit Chakravarty
    Efficient Implication - Based Untestable Bridge Fault Identifier. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:393-402 [Conf]
  44. Eric N. Tran, Vishwashanth Kasulasrinivas, Sreejit Chakravarty
    Silicon Evaluation of Logic Proximity Bridge Patterns. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:78-85 [Conf]
  45. Sreejit Chakravarty, Ramalingam Sridhar, Shambhu J. Upadhyaya, Yervant Zorian, Gil Philips, Bozena Kaminska, Bernard Courtois
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:4, pp:95-97 [Journal]
  46. Sreejit Chakravarty
    A Characterization of Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:2, pp:129-137 [Journal]
  47. Sreejit Chakravarty
    A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:8, pp:985-991 [Journal]
  48. Sreejit Chakravarty, Harry B. Hunt III
    A Note on Detecting Sneak Paths in Transistor Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:6, pp:861-864 [Journal]
  49. Sreejit Chakravarty, Harry B. Hunt III
    On Computing Signal Probability and Detection Probability of Stuck-at Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:11, pp:1369-1377 [Journal]
  50. Sreejit Chakravarty, Harry B. Hunt III, S. S. Ravi, Daniel J. Rosenkrantz
    The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:6, pp:865-869 [Journal]
  51. Sreejit Chakravarty, Paul J. Thadikaran
    Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:10, pp:1131-1140 [Journal]
  52. Sreejit Chakravarty
    On the complexity of computing tests for CMOS gates. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:973-980 [Journal]
  53. Sreejit Chakravarty, Xin He, S. S. Ravi
    Minimum area layout of series-parallel transistor networks is NP-hard. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:943-949 [Journal]
  54. Sreejit Chakravarty, S. S. Ravi
    Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:3, pp:329-331 [Journal]
  55. Sreejit Chakravarty, Sujit T. Zachariah
    STBM: a fast algorithm to simulate IDDQ tests forleakage faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:568-576 [Journal]
  56. Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy
    Techniques for minimizing power dissipation in scan and combinational circuits during test application. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1325-1333 [Journal]
  57. Yiming Gong, Sreejit Chakravarty
    Locating bridging faults using dynamically computed stuck-at fault dictionaries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:876-887 [Journal]
  58. Sujit T. Zachariah, Sreejit Chakravarty
    Extraction of two-node bridges from large industrial circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:433-439 [Journal]
  59. Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty
    Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:4, pp:471-489 [Journal]
  60. Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran
    Efficient techniques for transition testing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:2, pp:258-278 [Journal]
  61. Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel
    Algorithms to compute bridging fault coverage of IDDQ test sets. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:3, pp:281-305 [Journal]
  62. Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty
    Automatic generation and compaction of March tests for memory arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:845-857 [Journal]
  63. Sujit T. Zachariah, Sreejit Chakravarty
    Algorithm to extract two-node bridges. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:741-744 [Journal]

  64. Path selection for monitoring unexpected systematic timing effects. [Citation Graph (, )][DBLP]


  65. Detectability of internal bridging faults in scan chains. [Citation Graph (, )][DBLP]


  66. Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. [Citation Graph (, )][DBLP]


  67. Improving the Detectability of Resistive Open Faults in Scan Cells. [Citation Graph (, )][DBLP]


  68. An Enhanced Logic BIST Architecture for Online Testing. [Citation Graph (, )][DBLP]


  69. An Industrial Case Study of Sticky Path-Delay Faults. [Citation Graph (, )][DBLP]


  70. On the Detectability of Scan Chain Internal Faults — An Industrial Case Study. [Citation Graph (, )][DBLP]


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