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Ismet Bayraktaroglu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ismet Bayraktaroglu, Alex Orailoglu
    Accumulation-based concurrent fault detection for linear digital state variable systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:484-0 [Conf]
  2. Ismet Bayraktaroglu, Alex Orailoglu
    Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck? [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:373-378 [Conf]
  3. Ismet Bayraktaroglu, K. Udawatta, Alex Orailoglu
    An Examination of PRPG Selection Approaches for Large, Industrial Designs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:440-0 [Conf]
  4. Ismet Bayraktaroglu, Alex Orailoglu
    Improved fault diagnosis in scan-based BIST via superposition. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:55-58 [Conf]
  5. Ismet Bayraktaroglu, Alex Orailoglu
    Test Volume and Application Time Reduction Through Scan Chain Concealment. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:151-155 [Conf]
  6. Wenjing Rao, Ismet Bayraktaroglu, Alex Orailoglu
    Test application time and volume compression through seed overlapping. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:732-737 [Conf]
  7. Ismet Bayraktaroglu, Alex Orailoglu
    Diagnosis for scan-based BIST: reaching deep into the signatures. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:102-111 [Conf]
  8. Ismet Bayraktaroglu, Alex Orailoglu
    Gate Level Fault Diagnosis in Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:376-381 [Conf]
  9. Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu
    Test Synthesis for Mixed-Signal SOC Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:128-133 [Conf]
  10. Ismet Bayraktaroglu, Alex Orailoglu
    Deterministic partitioning techniques for fault diagnosis in scan-based BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:273-282 [Conf]
  11. Olivier Caty, Ismet Bayraktaroglu, Amitava Majumdar, Richard Lee, John Bell, Lisa Curhan
    Instruction Based BIST for Board/System Level Test of External Memories and Internconnects. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:961-970 [Conf]
  12. Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
    Scan Power Reduction Through Test Data Transition Frequency Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:844-850 [Conf]
  13. Ismet Bayraktaroglu, Alex Orailoglu
    Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:113-120 [Conf]
  14. Ismet Bayraktaroglu, Alex Orailoglu
    Low-Cost On-Line Test for Digital Filters. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:446-451 [Conf]
  15. Ismet Bayraktaroglu, Olivier Caty, Yickkei Wong
    Highly Configurable Programmable Built-In Self Test Architecture for High-Speed Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:21-26 [Conf]
  16. Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu
    Invariance-Based On-Line Test for RTL Controller-Datapath Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:459-464 [Conf]
  17. Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
    Test Power Reduction through Minimization of Scan Chain Transitions. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:166-172 [Conf]
  18. Ismet Bayraktaroglu, Alex Orailoglu
    Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:1, pp:42-53 [Journal]
  19. Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu
    Seamless Test of Digital Components in Mixed-Signal Paths. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:1, pp:44-55 [Journal]
  20. Ismet Bayraktaroglu, Arif Selçuk Ögrenci, Günhan Dündar, Sina Balkir, Ethem Alpaydin
    ANNSyS: an Analog Neural Network Synthesis System. [Citation Graph (0, 0)][DBLP]
    Neural Networks, 1999, v:12, n:2, pp:325-338 [Journal]
  21. Ismet Bayraktaroglu, Alex Orailoglu
    Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:11, pp:1480-1489 [Journal]
  22. Ismet Bayraktaroglu, Alex Orailoglu
    The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:1, pp:61-75 [Journal]
  23. Ismet Bayraktaroglu, Alex Orailoglu
    Concurrent test for digital linear systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1132-1142 [Journal]
  24. Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu
    Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2004, v:53, n:2, pp:269-278 [Journal]

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