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Stefano Di Carlo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    Memory Read Faults: Taxonomy and Automatic Test Generation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:157-163 [Conf]
  2. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    Specification and Design of a New Memory Fault Simulator. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:92-97 [Conf]
  3. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Luca Tagliaferri
    Control-Flow Checking via Regular Expressions. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:299-303 [Conf]
  4. Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    Automatic march tests generations for static linked faults in SRAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1258-1263 [Conf]
  5. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    SEU effect analysis in an open-source router via a distributed fault injection environment. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:219-225 [Conf]
  6. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    An Optimal Algorithm for the Automatic Generation of March Tests. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:938-943 [Conf]
  7. Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Hans-Joachim Wunderlich
    On applying the set covering model to reseeding. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:156-161 [Conf]
  8. Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:157-158 [Conf]
  9. Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    Automatic March Tests Generation for Multi-Port SRAMs. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:385-392 [Conf]
  10. Marie-Lise Flottes, Yves Bertrand, L. Balado, E. Lupon, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich
    Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:135-139 [Conf]
  11. Alfredo Benso, Stefano Di Carlo, Silvia Chiusano, Paolo Prinetto, Fabio Ricciato, Monica Lobetti Bodoni, Maurizio Spadari
    On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:539-540 [Conf]
  12. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    A Watchdog Processor to Detect Data and Control Flow Errors. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:144-148 [Conf]
  13. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, I. Solcia, Luca Tagliaferri
    FAUST: FAUlt-injection Script-based Tool. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:160- [Conf]
  14. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Luca Tagliaferri, Paolo Prinetto
    Validation of a Software Dependability Tool via Fault Injection Experiments. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:3-8 [Conf]
  15. Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto
    Automated Synthesis of SEU Tolerant Architectures from OO Descriptions. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:26-31 [Conf]
  16. Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Fabio Ricciato, Maurizio Spadari, Yervant Zorian
    HD/sup 2/BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:892-901 [Conf]
  17. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    Static Analysis of SEU Effects on Software Applications. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:500-508 [Conf]
  18. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni
    A programmable BIST architecture for clusters of multiple-port SRAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:557-566 [Conf]
  19. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Luca Tagliaferri
    Data Critically Estimation In Software Applications. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:802-810 [Conf]
  20. Yves Bertrand, Marie-Lise Flottes, L. Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich, J.-P. Van der Heyden
    Test Engineering Education in Europe: the EuNICE-Test Project. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:85-86 [Conf]
  21. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    Online Self-Repair of FIR Filters. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:3, pp:50-57 [Journal]
  22. Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian
    A Hierarchical Infrastructure for SoC Test Management. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:4, pp:32-39 [Journal]
  23. Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale
    Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:205-206 [Conf]
  24. Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto
    Single-Event Upset Analysis and Protection in High Speed Circuits. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:29-34 [Conf]
  25. Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    A 22n March Test for Realistic Static Linked Faults in SRAMs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:49-54 [Conf]

  26. A FPGA-Based Reconfigurable Software Architecture for Highly Dependable Systems. [Citation Graph (, )][DBLP]


  27. Differential gene expression graphs: A data structure for classification in DNA microarrays. [Citation Graph (, )][DBLP]


  28. A graph-based representation of Gene Expression profiles in DNA microarrays. [Citation Graph (, )][DBLP]


  29. Test exploration and validation using transaction level models. [Citation Graph (, )][DBLP]


  30. A Functional Verification Based Fault Injection Environment. [Citation Graph (, )][DBLP]


  31. System Level Testing via TLM 2.0 Debug Transport Interface. [Citation Graph (, )][DBLP]


  32. Exploiting Evolution for an Adaptive Drift-Robust Classifier in Chemical Sensing. [Citation Graph (, )][DBLP]


  33. Microprocessor fault-tolerance via on-the-fly partial reconfiguration. [Citation Graph (, )][DBLP]


  34. Are IEEE-1500-Compliant Cores Really Compliant to the Standard?. [Citation Graph (, )][DBLP]


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