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Patrick Girard: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:253-258 [Conf]
  2. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
    Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:250-255 [Conf]
  3. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
    Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:266-271 [Conf]
  4. Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault
    A Ring Architecture Strategy for BIST Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:418-423 [Conf]
  5. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    An adjacency-based test pattern generator for low power BIST design. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:459-464 [Conf]
  6. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:89-94 [Conf]
  7. Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel
    A BIST Structure to Test Delay Faults in a Scan Environment. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:435-439 [Conf]
  8. Nicolas Guibert, Patrick Girard, Laurent Guittet
    Example-based programming: a pertinent visual approach for learning to program. [Citation Graph (0, 0)][DBLP]
    AVI, 2004, pp:358-361 [Conf]
  9. Guillaume Patry, Patrick Girard
    GIPSE, A Model-Based System for CAD Software. [Citation Graph (0, 0)][DBLP]
    CADUI, 1999, pp:61-72 [Conf]
  10. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
    Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:857-862 [Conf]
  11. Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    A Novel Approach to Delay-Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:357-360 [Conf]
  12. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Design of Routing-Constrained Low Power Scan Chains. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:62-67 [Conf]
  13. Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard
    Minimizing test power in SRAM through reduction of pre-charge activity. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1159-1164 [Conf]
  14. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
    March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:256-261 [Conf]
  15. Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    A Mixed Approach for Unified Logic Diagnosis. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:239-242 [Conf]
  16. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
    High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:83-88 [Conf]
  17. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Design of Routing-Constrained Low Power Scan Chains. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:287-294 [Conf]
  18. Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    Test Power: a Big Issue in Large SOC Designs. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:447-449 [Conf]
  19. Yamine Aït Ameur, Patrick Girard, Francis Jambon
    A Uniform Approach for Specification and Design of Interactive Systems: the B Method. [Citation Graph (0, 0)][DBLP]
    DSV-IS (2), 1998, pp:51-67 [Conf]
  20. Francis Jambon, Patrick Girard, Yohann Boisdron
    Dialogue Validation from Task Analysis. [Citation Graph (0, 0)][DBLP]
    DSV-IS, 1999, pp:205-224 [Conf]
  21. Yamine Aït Ameur, Patrick Girard, Francis Jambon
    Using the B Formal Approach for Incremental Specification Design of Interactiv Systems. [Citation Graph (0, 0)][DBLP]
    EHCI, 1998, pp:91-109 [Conf]
  22. Francis Jambon, Patrick Girard, Yamine Aït Ameur
    Interactive System Safety and Usability Enforced with the Development Process. [Citation Graph (0, 0)][DBLP]
    EHCI, 2001, pp:39-56 [Conf]
  23. D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:518-523 [Conf]
  24. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:24-0 [Conf]
  25. Guillaume Texier, Laurent Guittet, Patrick Girard
    The dialog tool set: a new way to create the dialog component. [Citation Graph (0, 0)][DBLP]
    HCI, 2001, pp:200-204 [Conf]
  26. René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Random Adjacent Sequences: An Efficient Solution for Logic BIST. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:413-424 [Conf]
  27. Yamine Aït Ameur, Benoit Breholée, Patrick Girard, Laurent Guittet, Francis Jambon
    Formal Verification and Validation of Interactive Systems Specifications. [Citation Graph (0, 0)][DBLP]
    Human Error, Safety and Systems Development, 2004, pp:61-76 [Conf]
  28. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
    Defect Analysis for Delay-Fault BIST in FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:124-128 [Conf]
  29. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
    BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:187-192 [Conf]
  30. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:121-126 [Conf]
  31. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    A Gated Clock Scheme for Low Power Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:87-89 [Conf]
  32. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, J. Figueras, S. Manich, P. Teixeira, M. Santos
    Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:110-113 [Conf]
  33. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac
    A gate resizing technique for high reduction in power consumption. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:281-286 [Conf]
  34. Patrick Girard
    Low Power Testing of VLSI Circuits: Problems and Solutions. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:173-180 [Conf]
  35. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:488-493 [Conf]
  36. Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    Power Driven Chaining of Flip-Flops in Scan Architectures. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:796-803 [Conf]
  37. D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:705-713 [Conf]
  38. Christophe Fagot, Patrick Girard, Christian Landrault
    On Using Machine Learning for Logic BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:338-346 [Conf]
  39. Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch
    Low power BIST design by hypergraph partitioning: methodology and architectures. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:652-661 [Conf]
  40. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
    A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:286-293 [Conf]
  41. Mickaël Baron, Patrick Girard
    SUIDT: safe user interface design tool. [Citation Graph (0, 0)][DBLP]
    Intelligent User Interfaces, 2004, pp:350-351 [Conf]
  42. Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault
    Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:540-549 [Conf]
  43. Yamine Aït Ameur, Frederic Besnard, Patrick Girard, Guy Pierra, Jean-Claude Potier
    Formal Specification and Metaprogramming in the EXPRESS Language. [Citation Graph (0, 0)][DBLP]
    SEKE, 1995, pp:181-188 [Conf]
  44. Yamine Aït Ameur, Mickaël Baron, Patrick Girard
    Formal Validation of HCI User Tasks. [Citation Graph (0, 0)][DBLP]
    Software Engineering Research and Practice, 2003, pp:732-738 [Conf]
  45. Benoit Boulet, Robert DiRaddo, Patrick Girard, Vince Thomson
    An agent based architecture for model based control. [Citation Graph (0, 0)][DBLP]
    SMC (2), 2004, pp:2002-2007 [Conf]
  46. Mickaël Baron, Patrick Girard
    SUIDT: A task model based GUI-Builder. [Citation Graph (0, 0)][DBLP]
    TAMODIA, 2002, pp:64-71 [Conf]
  47. Mickaël Baron, Patrick Girard
    Bringing Robustness to End-User Programming. [Citation Graph (0, 0)][DBLP]
    HCC, 2001, pp:142-0 [Conf]
  48. Guillaume Patry, Patrick Girard
    End-User Programming in a Structured Dialogue Environment: the GIPSE Project. [Citation Graph (0, 0)][DBLP]
    HCC, 2001, pp:212-0 [Conf]
  49. Laurent Bréhélin, Olivier Gascuel, Gilles Caraux, Patrick Girard, Christian Landrault
    Hidden Markov and Independence Models with Patterns for Sequential BIST. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:359-368 [Conf]
  50. O. Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    An Overview of Failure Mechanisms in Embedded Flash Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:108-113 [Conf]
  51. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    A Test Vector Inhibiting Technique for Low Energy BIST Design. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:407-412 [Conf]
  52. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich
    A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:306-311 [Conf]
  53. Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch
    An optimized BIST test pattern generator for delay testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:94-100 [Conf]
  54. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
    Diagnostic of path and gate delay faults in non-scan sequential circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:380-386 [Conf]
  55. S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    A new test pattern generation method for delay fault testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:296-301 [Conf]
  56. René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    On Using Efficient Test Sequences for BIST. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:145-152 [Conf]
  57. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
    March iC-: An Improved Version of March C- for ADOFs Detection. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:129-138 [Conf]
  58. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan
    Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:183-188 [Conf]
  59. O. Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:47-52 [Conf]
  60. A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
    Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:361-368 [Conf]
  61. Patrick Girard
    Survey of Low-Power Testing of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:3, pp:82-92 [Journal]
  62. Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    Delay-Fault Diagnosis by Critical-Path Tracing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:4, pp:27-32 [Journal]
  63. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich
    High Defect Coverage with Low-Power Test Sequences in a BIST Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:44-52 [Journal]
  64. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac
    A non-iterative gate resizing algorithm for high reduction in power consumption. [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:24, n:1, pp:37-52 [Journal]
  65. A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
    Slow write driver faults in 65nm SRAM technology: analysis and March test solution. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:528-533 [Conf]
  66. Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich
    Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:403-408 [Conf]
  67. Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault
    Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:267-281 [Conf]
  68. Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    DERRIC: A Tool for Unified Logic Diagnosis. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:13-20 [Conf]
  69. O. Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:77-84 [Conf]
  70. A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
    Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:97-104 [Conf]
  71. Patrick Girard, Yannick Bonhomme
    Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:1, pp:85-95 [Journal]
  72. Patrick Girard
    Welcome to the Journal of Low Power Electronics. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:1, pp:1-2 [Journal]
  73. Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard
    Reducing Power Dissipation in SRAM during Test. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:271-280 [Journal]
  74. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
    Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:5, pp:551-561 [Journal]
  75. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
    Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:1, pp:43-55 [Journal]
  76. Simone Borri, Magali Bastian Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
    Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:2, pp:169-179 [Journal]
  77. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    A Gated Clock Scheme for Low Power Testing of Logic Cores. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:1, pp:89-99 [Journal]
  78. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
    ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:3, pp:287-296 [Journal]
  79. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
    An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:2, pp:161-172 [Journal]

  80. Delay Fault Diagnosis in Sequential Circuits. [Citation Graph (, )][DBLP]


  81. A statistical simulation method for reliability analysis of SRAM core-cells. [Citation Graph (, )][DBLP]


  82. A Design-for-Diagnosis Technique for SRAM Write Drivers. [Citation Graph (, )][DBLP]


  83. Power-Aware Testing and Test Strategies for Low Power Devices. [Citation Graph (, )][DBLP]


  84. A new design-for-test technique for SRAM core-cell stability faults. [Citation Graph (, )][DBLP]


  85. An efficient fault simulation technique for transition faults in non-scan sequential circuits. [Citation Graph (, )][DBLP]


  86. SoC Symbolic Simulation: a case study on delay fault testing. [Citation Graph (, )][DBLP]


  87. Comprehensive bridging fault diagnosis based on the SLAT paradigm. [Citation Graph (, )][DBLP]


  88. Improving Diagnosis Resolution without Physical Information. [Citation Graph (, )][DBLP]


  89. An Exact and Efficient Critical Path Tracing Algorithm. [Citation Graph (, )][DBLP]


  90. Impact of Resistive-Bridging Defects in SRAM Core-Cell. [Citation Graph (, )][DBLP]


  91. Using TMR Architectures for Yield Improvement. [Citation Graph (, )][DBLP]


  92. Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric. [Citation Graph (, )][DBLP]


  93. Agent-Based Architecture for Interactive System Design: Current Approaches, Perspectives and Evaluation. [Citation Graph (, )][DBLP]


  94. Hierarchical Structure: A Step for Jointly Designing Interactive Software Dialog and Task Model. [Citation Graph (, )][DBLP]


  95. Energy Model based Control for Forming Processes. [Citation Graph (, )][DBLP]


  96. Yield Improvement, Fault-Tolerance to the Rescue?. [Citation Graph (, )][DBLP]


  97. A case study on logic diagnosis for System-on-Chip. [Citation Graph (, )][DBLP]


  98. Assessment of Object Use for Task Modeling. [Citation Graph (, )][DBLP]


  99. Generating Interactive Applications from Task Models: A Hard Challenge. [Citation Graph (, )][DBLP]


  100. Formally Expressing the Users' Objects World in Task Models. [Citation Graph (, )][DBLP]


  101. An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. [Citation Graph (, )][DBLP]


  102. Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. [Citation Graph (, )][DBLP]


  103. Setting test conditions for improving SRAM reliability. [Citation Graph (, )][DBLP]


  104. A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction. [Citation Graph (, )][DBLP]


  105. Comparaison de deux méthodes pour implémenter la programmation sur exemple. [Citation Graph (, )][DBLP]


  106. Validation d'une approche " basée sur exemples " pour l'apprentissage de la programmation. [Citation Graph (, )][DBLP]


  107. SUIDT: a user interface builder for secure user interfaces. [Citation Graph (, )][DBLP]


  108. Programming by example and computer-aided teaching of algorithmics: the MELBA project. [Citation Graph (, )][DBLP]


  109. An Analytic Logic of Aggregation. [Citation Graph (, )][DBLP]


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