The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Serge Pravossoudovitch: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:253-258 [Conf]
  2. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
    Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:250-255 [Conf]
  3. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
    Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:266-271 [Conf]
  4. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    An adjacency-based test pattern generator for low power BIST design. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:459-464 [Conf]
  5. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:89-94 [Conf]
  6. Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel
    A BIST Structure to Test Delay Faults in a Scan Environment. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:435-439 [Conf]
  7. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
    Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:857-862 [Conf]
  8. Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    A Novel Approach to Delay-Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:357-360 [Conf]
  9. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Design of Routing-Constrained Low Power Scan Chains. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:62-67 [Conf]
  10. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
    March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:256-261 [Conf]
  11. Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    A Mixed Approach for Unified Logic Diagnosis. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:239-242 [Conf]
  12. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
    High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:83-88 [Conf]
  13. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Design of Routing-Constrained Low Power Scan Chains. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:287-294 [Conf]
  14. Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    Test Power: a Big Issue in Large SOC Designs. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:447-449 [Conf]
  15. D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:518-523 [Conf]
  16. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:24-0 [Conf]
  17. René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Random Adjacent Sequences: An Efficient Solution for Logic BIST. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:413-424 [Conf]
  18. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
    Defect Analysis for Delay-Fault BIST in FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:124-128 [Conf]
  19. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
    BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:187-192 [Conf]
  20. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:121-126 [Conf]
  21. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    A Gated Clock Scheme for Low Power Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:87-89 [Conf]
  22. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, J. Figueras, S. Manich, P. Teixeira, M. Santos
    Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:110-113 [Conf]
  23. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac
    A gate resizing technique for high reduction in power consumption. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:281-286 [Conf]
  24. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:488-493 [Conf]
  25. Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    Power Driven Chaining of Flip-Flops in Scan Architectures. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:796-803 [Conf]
  26. D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:705-713 [Conf]
  27. Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch
    Low power BIST design by hypergraph partitioning: methodology and architectures. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:652-661 [Conf]
  28. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
    A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:286-293 [Conf]
  29. Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault
    Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:540-549 [Conf]
  30. O. Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    An Overview of Failure Mechanisms in Embedded Flash Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:108-113 [Conf]
  31. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    A Test Vector Inhibiting Technique for Low Energy BIST Design. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:407-412 [Conf]
  32. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich
    A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:306-311 [Conf]
  33. Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch
    An optimized BIST test pattern generator for delay testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:94-100 [Conf]
  34. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
    Diagnostic of path and gate delay faults in non-scan sequential circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:380-386 [Conf]
  35. S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    A new test pattern generation method for delay fault testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:296-301 [Conf]
  36. René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    On Using Efficient Test Sequences for BIST. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:145-152 [Conf]
  37. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
    March iC-: An Improved Version of March C- for ADOFs Detection. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:129-138 [Conf]
  38. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan
    Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:183-188 [Conf]
  39. O. Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:47-52 [Conf]
  40. A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
    Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:361-368 [Conf]
  41. Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    Delay-Fault Diagnosis by Critical-Path Tracing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:4, pp:27-32 [Journal]
  42. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich
    High Defect Coverage with Low-Power Test Sequences in a BIST Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:44-52 [Journal]
  43. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac
    A non-iterative gate resizing algorithm for high reduction in power consumption. [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:24, n:1, pp:37-52 [Journal]
  44. A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
    Slow write driver faults in 65nm SRAM technology: analysis and March test solution. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:528-533 [Conf]
  45. Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich
    Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:403-408 [Conf]
  46. Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault
    Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:267-281 [Conf]
  47. Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    DERRIC: A Tool for Unified Logic Diagnosis. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:13-20 [Conf]
  48. O. Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:77-84 [Conf]
  49. A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
    Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:97-104 [Conf]
  50. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
    Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:5, pp:551-561 [Journal]
  51. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
    Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:1, pp:43-55 [Journal]
  52. Simone Borri, Magali Bastian Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
    Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:2, pp:169-179 [Journal]
  53. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    A Gated Clock Scheme for Low Power Testing of Logic Cores. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:1, pp:89-99 [Journal]
  54. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
    ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:3, pp:287-296 [Journal]
  55. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
    An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:2, pp:161-172 [Journal]

  56. Delay Fault Diagnosis in Sequential Circuits. [Citation Graph (, )][DBLP]


  57. A statistical simulation method for reliability analysis of SRAM core-cells. [Citation Graph (, )][DBLP]


  58. A Design-for-Diagnosis Technique for SRAM Write Drivers. [Citation Graph (, )][DBLP]


  59. A new design-for-test technique for SRAM core-cell stability faults. [Citation Graph (, )][DBLP]


  60. An efficient fault simulation technique for transition faults in non-scan sequential circuits. [Citation Graph (, )][DBLP]


  61. SoC Symbolic Simulation: a case study on delay fault testing. [Citation Graph (, )][DBLP]


  62. Comprehensive bridging fault diagnosis based on the SLAT paradigm. [Citation Graph (, )][DBLP]


  63. Improving Diagnosis Resolution without Physical Information. [Citation Graph (, )][DBLP]


  64. An Exact and Efficient Critical Path Tracing Algorithm. [Citation Graph (, )][DBLP]


  65. Impact of Resistive-Bridging Defects in SRAM Core-Cell. [Citation Graph (, )][DBLP]


  66. Using TMR Architectures for Yield Improvement. [Citation Graph (, )][DBLP]


  67. Fault modelling and fault equivalence in CMOS technology. [Citation Graph (, )][DBLP]


  68. Yield Improvement, Fault-Tolerance to the Rescue?. [Citation Graph (, )][DBLP]


  69. A case study on logic diagnosis for System-on-Chip. [Citation Graph (, )][DBLP]


  70. An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. [Citation Graph (, )][DBLP]


  71. Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. [Citation Graph (, )][DBLP]


  72. Setting test conditions for improving SRAM reliability. [Citation Graph (, )][DBLP]


  73. A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction. [Citation Graph (, )][DBLP]


Search in 0.171secs, Finished in 0.175secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002