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Publications of Author

1. Soumitra Bose, Vishwani D. Agrawal
   Sequential logic path delay test generation by symbolic analysis. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1995, pp:353-0 [Conf]
   
2. P. E. Allen, Soumitra Bose, Edmund M. Clarke, Spiro Michaylov
   PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses. [Citation Graph (0, 0)][DBLP]
   CADE, 1988, pp:764-765 [Conf]
   
3. Soumitra Bose, Prathima Agrawal
   Concurrent Fault Simulation of Logic Gates and Memory Blocks on Message Passing Multicomputers. [Citation Graph (0, 0)][DBLP]
   DAC, 1992, pp:332-335 [Conf]
   
4. Soumitra Bose
   Automated Modeling of Custom Digital Circuits for Test. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:954-963 [Conf]
   
5. Soumitra Bose, Amit Nandi
   Extraction of Schematic Array Models for Memory Circuits. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:570-577 [Conf]
   
6. Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
   Generation of Compact Delay Tests by Multiple-Path Activation. [Citation Graph (0, 0)][DBLP]
   ITC, 1993, pp:714-723 [Conf]
   
7. Soumitra Bose, Vishwani D. Agrawal, Thomas G. Szymanski
   Algorithms for Switch Level Delay Fault Simulation. [Citation Graph (0, 0)][DBLP]
   ITC, 1997, pp:982-991 [Conf]
   
8. Soumitra Bose, Edmund M. Clarke, David E. Long, Spiro Michaylov
   PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses [Citation Graph (0, 0)][DBLP]
   LICS, 1989, pp:80-89 [Conf]
   
9. Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
   A Path Delay Fault Simulator for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1993, pp:269-274 [Conf]
   
10. Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram
    Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:88-93 [Conf]
    
11. Soumitra Bose, Vishwani D. Agrawal
    Delay Test Quality Evaluation Using Bounded Gate Delays. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:23-28 [Conf]
    
12. Soumitra Bose, Edmund M. Clarke, David E. Long, Spiro Michaylov
    PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses. [Citation Graph (0, 0)][DBLP]
    J. Autom. Reasoning, 1992, v:8, n:2, pp:153-181 [Journal]
    
13. Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
    Deriving Logic Systems for Path Delay Test Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:8, pp:829-846 [Journal]
    
14. Soumitra Bose, Amit Nandi
    Schematic array models for associative and non-associative memory circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1582-1593 [Journal]
    
15. Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
    Path delay fault simulation of sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:453-461 [Journal]