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Parag K. Lala: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Fadi Y. Busaba, Parag K. Lala
    A graph coloring based approach for self-checking logic circuit design. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:327-0 [Conf]
  2. Parag K. Lala, Alvernon Walker
    A Unified Scheme for Designing Testable State Machines. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:273-278 [Conf]
  3. D. P. Vasudevan, Parag K. Lala, James Patrick Parkerson
    A Novel Approach for On-line Testable Reversible Logic Circuit Desig. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:325-330 [Conf]
  4. D. P. Vasudevan, Parag K. Lala
    A New Reversible Logic Gate and its Applications. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:480-484 [Conf]
  5. Parag K. Lala, K. K. Bondali
    On Biologically-Inspired Design of Fault-Tolerant Digital Systems. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:287-290 [Conf]
  6. Jia Di, Parag K. Lala, D. P. Vasudevan
    On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:371-379 [Conf]
  7. Parag K. Lala
    A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:235-241 [Conf]
  8. Parag K. Lala, Anup Singh, Alvernon Walker
    A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:238-246 [Conf]
  9. Parag K. Lala, Alvernon Walker
    An On-Line Reconfigurable FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:275-0 [Conf]
  10. Parag K. Lala, Alvernon Walker
    On-Line Error Detectable Carry-Free Adder Design. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:66-71 [Conf]
  11. D. P. Vasudevan, Parag K. Lala
    A Technique for Modular Design of Self-Checking Carry-Select Adder. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:325-333 [Conf]
  12. D. P. Vasudevan, Parag K. Lala, James Patrick Parkerson
    Online Testable Reversible Logic Circuit Design using NAND Blocks. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:324-331 [Conf]
  13. Alvernon Walker, Algernon P. Henry, Parag K. Lala
    An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:272-280 [Conf]
  14. Parag K. Lala, A. L. Burress
    Self-Checking Logic Design for LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:253- [Conf]
  15. Parag K. Lala, B. Kiran Kumar
    An FPGA architecture with built-in error correction capability. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:245- [Conf]
  16. Parag K. Lala, Mark G. Karpovsky
    An Approach for Designing On-Line Testable State Machines. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:135- [Conf]
  17. Parag K. Lala, B. Kiran Kumar
    An Architecture for Self-Healing Digital Systems. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:3-7 [Conf]
  18. S. R. Seward, Parag K. Lala
    Fault Injection in Digital Logic Circuits at the VHDL Level. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:161- [Conf]
  19. Whitney J. Townsend, Jacob A. Abraham, Parag K. Lala
    On-Line Error Detecting Constant Delay Adder. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:17-0 [Conf]
  20. Parag K. Lala, A. L. Burress
    A technique for designing self-checking logic for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:94-96 [Conf]
  21. Jong O. Kim, Parag K. Lala, Young Gun Kim, Heung-Soo Kim
    Fault Analysis of the Multiple Valued Logic Using Spectral Method. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:59-0 [Conf]
  22. Parag K. Lala, B. Kiran Kumar
    Human Immune System Inspired Architecture for Self-Healing Digital Systems. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:292-297 [Conf]
  23. C. K. Tang, Parag K. Lala, James Patrick Parkerson
    A Technique for Designing Totally Self-Checking Domino Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:128-132 [Conf]
  24. Alvernon Walker, Parag K. Lala
    A Transition Based BIST Approach for Passive Analog Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:347-354 [Conf]
  25. D. P. Vasudevan, Parag K. Lala, James Patrick Parkerson
    CMOS Realization of Online Testable Reversible Logic Gates. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:309-310 [Conf]
  26. A. L. Burress, Parag K. Lala
    On-Line Testable Logic Desgin for FPGA Implementation. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:471-478 [Conf]
  27. B. Kiran Kumar, Parag K. Lala
    On-line Detection of Faults in Carry-Select Adders. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:912-918 [Conf]
  28. Parag K. Lala
    On Built-In Testing of VLSI Chips. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:719-721 [Conf]
  29. S. R. Seward, Parag K. Lala
    Fault Injection for Verifying Testability at the VHDL Level. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:131-137 [Conf]
  30. D. L. Tao, Carlos R. P. Hartmann, Parag K. Lala
    A Concurrent Testing Strategy for PLAs. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:705-709 [Conf]
  31. Whitney J. Townsend, Mitchell A. Thornton, Parag K. Lala
    On-line Error Detection in a Carry-free Adder. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:251-254 [Conf]
  32. D. P. Vasudevan, James Patrick Parkerson, Parag K. Lala
    Logic implementation using a reversible gate. [Citation Graph (0, 0)][DBLP]
    Circuits, Signals, and Systems, 2004, pp:452-456 [Conf]
  33. Alvernon Walker, Winser E. Alexander, Parag K. Lala
    Fault Diagnosis in Analog Circuits Using Element Modulation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:1, pp:19-29 [Journal]
  34. K. Lai, Parag K. Lala
    Multiple Fault Detection in Fan-Out Free Circuits Using Minimal Single Fault Test Set. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:6, pp:763-765 [Journal]
  35. D. L. Tao, Carlos R. P. Hartmann, Parag K. Lala
    A Note on t-EC/d-UED Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:5, pp:660-663 [Journal]
  36. D. L. Tao, Carlos R. P. Hartmann, Parag K. Lala
    A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:7, pp:881-886 [Journal]
  37. J. Q. Wang, Parag K. Lala
    Partially Strongly Fault Secure and Partially Strongly Code Disjoint I-out-of-3 Code Checker. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:10, pp:1238-1240 [Journal]
  38. Parag K. Lala, B. Kiran Kumar, J. P. Parkerson
    On self-healing digital system design. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:4, pp:353-362 [Journal]
  39. Jia Di, Parag K. Lala
    Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:2-3, pp:175-192 [Journal]

  40. On FPGA Design with Self-checking and Fault Tolerance Capability. [Citation Graph (, )][DBLP]


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