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Marcelo Lubaszewski: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski
    Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:96-0 [Conf]
  2. Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell
    TI-BIST: a temperature independent analog BIST for switched-capacitor filters. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:78-83 [Conf]
  3. Marcelo Lubaszewski
    Bridging the Gap between Microelectronics and Micromechanics Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:513- [Conf]
  4. Vladimir Székely, Márta Rencz, Jean-Michel Karam, Marcelo Lubaszewski, Bernard Courtois
    Thermal Monitoring Of Safety-Critical Integrated Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:282-288 [Conf]
  5. J. Velasco-Medina, Marcelo Lubaszewski, Michael Nicolaidis
    An Approach to the On-Line Testing of Operational Amplifiers. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:290-295 [Conf]
  6. Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno
    Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:62-63 [Conf]
  7. Érika F. Cota, Luigi Carro, Marcelo Lubaszewski
    A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:184-188 [Conf]
  8. Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu
    Test Planning and Design Space Exploration in a Core-Based Environment. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:478-485 [Conf]
  9. Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski
    Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:226-0 [Conf]
  10. Marcelo Lubaszewski, Érika F. Cota, Bernard Courtois
    Microsystems Testing: an Approach and Open Problems. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:524-0 [Conf]
  11. Marcelo Lubaszewski, Salvador Mir, Leandro Pulz
    ABILBO: Analog BuILt-in Block Observer. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:600-603 [Conf]
  12. Salvador Mir, Vladimir Kolarik, Marcelo Lubaszewski, C. Nielsen, Bernard Courtois
    Built-in self-test and fault diagnosis of fully differential analogue circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:486-490 [Conf]
  13. Meryem Marzouki, Marcelo Lubaszewski, Mohamed Hedi Touati
    Unifying test and diagnosis of interconnects and logic clusters in partial boundary scan boards. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:654-657 [Conf]
  14. Marcelo Lubaszewski, José Luis Huertas
    Test and Design-for-Test of Mixed-Signal Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IFIP Congress Tutorials, 2004, pp:183-212 [Conf]
  15. Luigi Carro, André C. Nácul, Daniel Janner, Marcelo Lubaszewski
    Built-in Test of Analog Non-Linear Circuits in a SOC Environment. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:437-448 [Conf]
  16. Tiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell
    Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:192-197 [Conf]
  17. Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski
    Testing the Configurable Analog Blocks of Field Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:893-902 [Conf]
  18. Benoît Charlot, Salvador Mir, Érika F. Cota, Marcelo Lubaszewski, Bernard Courtois
    Fault modeling of suspended thermal MEMS. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:319-328 [Conf]
  19. Érika F. Cota, Luigi Carro, Flávio Rech Wagner, Marcelo Lubaszewski
    Power-aware NoC Reuse on the Testing of Core-based Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:612-621 [Conf]
  20. Marcelo Lubaszewski, Bernard Courtois
    On the Design of Self-Checking Boundary Scannable Boards. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:372-381 [Conf]
  21. José Vicente Calvano, Marcelo Lubaszewski
    Designing for Test Analog Signal Processors for MEMS-Based Inertial Sensors. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:251-256 [Conf]
  22. Vinícius P. Correia, Marcelo Lubaszewski, André Inácio Reis
    SIFU! - A Didactic Stuck-at Fault Simulator. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:93-94 [Conf]
  23. Antonio Andrade Jr., Érika F. Cota, Marcelo Lubaszewski
    Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:105-110 [Conf]
  24. Margrit R. Krug, Marcelo de Souza Moraes, Marcelo S. Lubaszewski
    Using a software testing technique to identify registers for partial scan implementation. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:208-213 [Conf]
  25. Alexandre M. Amory, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes
    Reducing test time with processor reuse in network-on-chip based systems. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:111-116 [Conf]
  26. Carlos Roberto Moratelli, Érika F. Cota, Marcelo Lubaszewski
    A cryptography core tolerant to DFA fault attacks. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:190-195 [Conf]
  27. Marcelo Moraes, Érika F. Cota, Luigi Carro, Flávio Rech Wagner, Marcelo Lubaszewski
    A constraint-based solution for on-line testing of processors embedded in real-time applications. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:68-73 [Conf]
  28. Bernard Courtois, Jean-Michel Karam, Salvador Mir, Marcelo Lubaszewski, Vladimir Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner
    Design and Test of MEMs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:270-0 [Conf]
  29. José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski
    Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:319-324 [Conf]
  30. José Vicente Calvano, Vladimir Castro Alves, Antônio C. Mesquita, Marcelo Lubaszewski
    Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:201-206 [Conf]
  31. Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell
    An Approach to the Built-In Self-Test of Field Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:383-388 [Conf]
  32. Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell
    Functional Test of Field Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:326-333 [Conf]
  33. Érika F. Cota, Márcio Eduardo Kreutz, Cesar Albenes Zeferino, Luigi Carro, Marcelo Lubaszewski, Altamiro Amadeu Susin
    The Impact of NoC Reuse on the Testing of Core-based Systems. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:128-133 [Conf]
  34. Khaled Saab, Bozena Kaminska, Bernard Courtois, Marcelo Lubaszewski
    Frequency-based BIST for analog circuit testin. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:54-59 [Conf]
  35. Jean-Michel Karam, Marcelo Lubaszewski, S. Blanton, A. Richardson
    Testing MEMS. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:320-321 [Conf]
  36. Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell
    Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:389-394 [Conf]
  37. Alexandre M. Amory, Frederico Ferlini, Marcelo Lubaszewski, Fernando Moraes
    DfT for the Reuse of Networks-on-Chip as Test Access Mechanism. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:435-440 [Conf]
  38. Érika F. Cota, José Di Elias Domênico, Marcelo Lubaszewski
    A CAT Tool for Frequency-domain Testing and Diagnosis on Analog. [Citation Graph (0, 0)][DBLP]
    J. Braz. Comp. Soc., 1997, v:4, n:2, pp:- [Journal]
  39. Renato P. Ribas, André Inácio Reis, Marcelo Lubaszewski
    Concepção de Circuitos e Sistemas Integrados. [Citation Graph (0, 0)][DBLP]
    RITA, 2001, v:8, n:1, pp:7-21 [Journal]
  40. Marcelo Lubaszewski, Bernard Courtois
    A Reliable Fail-Safe System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:2, pp:236-241 [Journal]
  41. Vladimir Kolarik, Salvador Mir, Marcelo Lubaszewski, Bernard Courtois
    Analog checkers with absolute and relative tolerances. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:607-612 [Journal]
  42. Érika F. Cota, Luigi Carro, Marcelo Lubaszewski
    Reusing an on-chip network for the test of core-based systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:4, pp:471-499 [Journal]
  43. Antonio Andrade Jr., Gustavo Vieira, Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell
    Built-in self-test of global interconnects of field programmable analog arrays. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:12, pp:1112-1123 [Journal]
  44. Margrit R. Krug, Marcelo S. Lubaszewski, Marcelo de Souza Moraes
    Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:314-319 [Conf]
  45. Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes
    Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:213-218 [Conf]
  46. Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno
    Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  47. Marcelo Lubaszewski, Salvador Mir, Vladimir Kolarik, C. Nielsen, Bernard Courtois
    Design of self-checking fully differential circuits and boards. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:113-128 [Journal]
  48. Tiago R. Balen, Antonio Q. Andrade, Florence Azaïs, Marcelo Lubaszewski, Michel Renovell
    Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:2, pp:135-146 [Journal]
  49. Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell
    A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:1, pp:9-16 [Journal]

  50. Can Functional Test Achieve Low-cost Full Coverage of NoC Faults? [Citation Graph (, )][DBLP]


  51. Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults. [Citation Graph (, )][DBLP]


  52. A fault-tolerant, DFA-resistant AES core. [Citation Graph (, )][DBLP]


  53. A novel AES cryptographic core highly resistant to differential power analysis attacks. [Citation Graph (, )][DBLP]


  54. Resource-and-time-aware test strategy for configurable quaternary logic blocks. [Citation Graph (, )][DBLP]


  55. Design of an embedded system for the proactive maintenance of electrical valves. [Citation Graph (, )][DBLP]


  56. Increasing reliability of programmable mixed-signal systems by applying design diversity redundancy. [Citation Graph (, )][DBLP]


  57. Diagnosis of interconnect shorts in mesh NoCs. [Citation Graph (, )][DBLP]


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