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Érika F. Cota :
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Luigi Carro , Érika F. Cota , Marcelo Lubaszewski , Yves Bertrand , Florence Azaïs , Michel Renovell TI-BIST: a temperature independent analog BIST for switched-capacitor filters. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2000, pp:78-83 [Conf ] Érika F. Cota , Luigi Carro , Marcelo Lubaszewski A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester. [Citation Graph (0, 0)][DBLP ] DATE, 1999, pp:184-188 [Conf ] Érika F. Cota , Luigi Carro , Marcelo Lubaszewski , Alex Orailoglu Test Planning and Design Space Exploration in a Core-Based Environment. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:478-485 [Conf ] Érika F. Cota , Michel Renovell , Florence Azaïs , Yves Bertrand , Luigi Carro , Marcelo Lubaszewski Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. [Citation Graph (0, 0)][DBLP ] DATE, 2000, pp:226-0 [Conf ] Marcelo Lubaszewski , Érika F. Cota , Bernard Courtois Microsystems Testing: an Approach and Open Problems. [Citation Graph (0, 0)][DBLP ] DATE, 1998, pp:524-0 [Conf ] Arthur Pereira Frantz , Luigi Carro , Érika F. Cota , Fernanda Lima Kastensmidt Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers. [Citation Graph (0, 0)][DBLP ] IOLTS, 2006, pp:191-192 [Conf ] Benoît Charlot , Salvador Mir , Érika F. Cota , Marcelo Lubaszewski , Bernard Courtois Fault modeling of suspended thermal MEMS. [Citation Graph (0, 0)][DBLP ] ITC, 1999, pp:319-328 [Conf ] Érika F. Cota , Luigi Carro , Flávio Rech Wagner , Marcelo Lubaszewski Power-aware NoC Reuse on the Testing of Core-based Systems. [Citation Graph (0, 0)][DBLP ] ITC, 2003, pp:612-621 [Conf ] Chunsheng Liu , Hamid Sharif , Érika F. Cota , Dhiraj K. Pradhan Test Scheduling for Network-on-Chip with BIST and Precedence Constraints. [Citation Graph (0, 0)][DBLP ] ITC, 2004, pp:1369-1378 [Conf ] Arthur Pereira Frantz , Fernanda Lima Kastensmidt , Luigi Carro , Érika F. Cota Evaluation of SEU and crosstalk effects in network-on-chip switches. [Citation Graph (0, 0)][DBLP ] SBCCI, 2006, pp:202-207 [Conf ] Antonio Andrade Jr. , Érika F. Cota , Marcelo Lubaszewski Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST. [Citation Graph (0, 0)][DBLP ] SBCCI, 2004, pp:105-110 [Conf ] Alexandre M. Amory , Érika F. Cota , Marcelo Lubaszewski , Fernando Gehm Moraes Reducing test time with processor reuse in network-on-chip based systems. [Citation Graph (0, 0)][DBLP ] SBCCI, 2004, pp:111-116 [Conf ] Carlos Roberto Moratelli , Érika F. Cota , Marcelo Lubaszewski A cryptography core tolerant to DFA fault attacks. [Citation Graph (0, 0)][DBLP ] SBCCI, 2006, pp:190-195 [Conf ] Marcelo Moraes , Érika F. Cota , Luigi Carro , Flávio Rech Wagner , Marcelo Lubaszewski A constraint-based solution for on-line testing of processors embedded in real-time applications. [Citation Graph (0, 0)][DBLP ] SBCCI, 2005, pp:68-73 [Conf ] Érika F. Cota , Márcio Eduardo Kreutz , Cesar Albenes Zeferino , Luigi Carro , Marcelo Lubaszewski , Altamiro Amadeu Susin The Impact of NoC Reuse on the Testing of Core-based Systems. [Citation Graph (0, 0)][DBLP ] VTS, 2003, pp:128-133 [Conf ] Chunsheng Liu , Vikram Iyengar , Jiangfan Shi , Érika F. Cota Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking. [Citation Graph (0, 0)][DBLP ] VTS, 2005, pp:349-354 [Conf ] Érika F. Cota , José Di Elias Domênico , Marcelo Lubaszewski A CAT Tool for Frequency-domain Testing and Diagnosis on Analog. [Citation Graph (0, 0)][DBLP ] J. Braz. Comp. Soc., 1997, v:4, n:2, pp:- [Journal ] Érika F. Cota , Chunsheng Liu Constraint-Driven Test Scheduling for NoC-Based Systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2465-2478 [Journal ] Érika F. Cota , Luigi Carro , Marcelo Lubaszewski Reusing an on-chip network for the test of core-based systems. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:4, pp:471-499 [Journal ] Embedded software testing: What kind of problem is this? [Citation Graph (, )][DBLP ] Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults. [Citation Graph (, )][DBLP ] A fault-tolerant, DFA-resistant AES core. [Citation Graph (, )][DBLP ] Improving the Test of NoC-Based SoCs with Help of Compression Schemes. [Citation Graph (, )][DBLP ] Analysis of the use of declarative languages for enhanced embedded system software development. [Citation Graph (, )][DBLP ] Resource-and-time-aware test strategy for configurable quaternary logic blocks. [Citation Graph (, )][DBLP ] Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router. [Citation Graph (, )][DBLP ] Diagnosis of interconnect shorts in mesh NoCs. [Citation Graph (, )][DBLP ] Crosstalk- and SEU-Aware Networks on Chips. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.304secs