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Yervant Zorian: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tsin-Yuan Chang, Yervant Zorian
    SoC Testing and P1500 Standard. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:492-0 [Conf]
  2. Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
    An effective BIST scheme for carry-save and carry-propagate array multipliers. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:298-302 [Conf]
  3. Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
    TOF: a tool for test pattern generation optimization of an FPGA application oriented test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:323-328 [Conf]
  4. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:254-0 [Conf]
  5. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:266-271 [Conf]
  6. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    Minimizing the Number of Test Configurations for Different FPGA Families. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:363-368 [Conf]
  7. Yervant Zorian
    Leveraging Infrastructure IP for SoC Yield. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:3-5 [Conf]
  8. Yervant Zorian, Juan Antonio Carballo
    T1: Design for Manufacturability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:- [Conf]
  9. Nic Mokhoff, Yervant Zorian
    Tradeoffs and choices for emerging SoCs in high-end applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:273- [Conf]
  10. Nic Mokhoff, Yervant Zorian, Kamalesh N. Ruparel, Hao Nham, Francesco Pessolano, Kee Sup Kim
    How to determine the necessity for emerging solutions. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:274-275 [Conf]
  11. Dennis Wassung, Yervant Zorian, Magdy S. Abadir, Mark Bapst, Colin Harris
    Choosing flows and methodologies for SoC design. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:167- [Conf]
  12. Ron Wilson, Yervant Zorian
    Decision-making for complex SoCs in consumer electronic products. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:173- [Conf]
  13. Yervant Zorian
    Embedding infrastructure IP for SOC yield improvement. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:709-712 [Conf]
  14. Yervant Zorian
    System-Chip Test Strategies (Tutorial). [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:752-757 [Conf]
  15. Yervant Zorian, Erik Jan Marinissen
    System chip test: how will it impact your design? [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:136-141 [Conf]
  16. T. Bogue, Michael Gössel, Helmut Jürgensen, Yervant Zorian
    Built-In Self-Test with an Alternating Output. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:180-0 [Conf]
  17. Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian
    Effective Low Power BIST for Datapaths. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:757- [Conf]
  18. Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian
    Effective Software Self-Test Methodology for Processor Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:592-597 [Conf]
  19. Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
    Low-Cost Software-Based Self-Testing of RISC Processor Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10714-10719 [Conf]
  20. Erik Jan Marinissen, Betty Prince, Doris Keitel-Schulz, Yervant Zorian
    Challenges in Embedded Memory Design and Test. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:722-727 [Conf]
  21. Cecilia Metra, Michel Renovell, G. Mojoli, Jean Michel Portal, S. Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi
    Novel Technique for Testing FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:89-0 [Conf]
  22. Michael Nicolaidis, Yervant Zorian
    Scaling Deeper to Submicron: On-Line Testing to the Rescue. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:432-0 [Conf]
  23. Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Yervant Zorian
    Deterministic software-based self-testing of embedded processor cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:92-96 [Conf]
  24. Antonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian
    An Effective BIST Architecture for Fast Multiplier Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:117-121 [Conf]
  25. Irith Pomeranz, Yervant Zorian
    Fault Isolation Using Tests for Non-Isolated Blocks. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1123- [Conf]
  26. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    RAM-Based FPGA's: A Test Approach for the Configurable Logic. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:82-88 [Conf]
  27. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:618-622 [Conf]
  28. Yervant Zorian
    Yield Improvement and Repair Trade-Off for Large Embedded Memories. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:69-70 [Conf]
  29. Yervant Zorian, Bill Frerichs, Dennis Wassung, Jim Ensel, Guri Stark, Mike Gianfagna, Kamalesh N. Ruparel
    Semiconductor Industry Disaggregation vs Reaggregation: Who Will be the Shark? [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:572- [Conf]
  30. Yervant Zorian, Michael Nicolaidis, Peter Muhmenthaler, David Y. Lepejian, Chris W. H. Strolenberg, Kees Veelenturf
    Tutorial Statement. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:66- [Conf]
  31. Yervant Zorian, Paolo Prinetto, João Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, O. P. Dias, Jorge Semião, Peter Muhmenthaler, W. Radermacher
    Embedded tutorial: TRP: integrating embedded test and ATE. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:34-37 [Conf]
  32. Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian
    Minimal March-Based Fault Location Algorithm with Partial Diagnosis for all Static Faults in Random Access Memories. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:262-267 [Conf]
  33. Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian
    A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:145-148 [Conf]
  34. Michel Renovell, Penelope Faure, Paolo Prinetto, Yervant Zorian
    Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:297-301 [Conf]
  35. A. J. van de Goor, Yervant Zorian, Ivo Schanstra
    Functional Tests for Ring-Address SRAM-type FIFOs. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:666- [Conf]
  36. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:139-148 [Conf]
  37. Yervant Zorian, André Ivanov
    Programmable Space Compaction for BIST. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:340-349 [Conf]
  38. Sujit Dey, Jacob A. Abraham, Yervant Zorian
    High-level design validation and test. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:3- [Conf]
  39. André Ivanov, Yervant Zorian
    Computing the Error Escape Probability in Count-Based Compaction Schemes. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:368-371 [Conf]
  40. Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian
    Synthesis of BIST hardware for performance testing of MCM interconnections. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:69-73 [Conf]
  41. Yervant Zorian, Sujit Dey, Mike Rodgers
    Test of Future System-on-Chips. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:392-398 [Conf]
  42. Yervant Zorian
    A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary-Scan. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:59-66 [Conf]
  43. Yervant Zorian, Valery A. Vardanian, K. Aleksanyan, K. Amirkhanyan
    Impact of Soft Error Challenge on SoC Design. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:63-68 [Conf]
  44. Régis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert
    On-Line Testing for Secure Implementations: Design and Validation. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:211- [Conf]
  45. Valery A. Vardanian, Yervant Zorian
    A March-Based Fault Location Algorithm for Static Random Access Memories. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:256-261 [Conf]
  46. Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
    An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:343-349 [Conf]
  47. Yervant Zorian
    Embedded-Quality for Test. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:211-212 [Conf]
  48. Yervant Zorian
    System-on-Chip: Embedded Test Strategies. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:7- [Conf]
  49. Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Fabio Ricciato, Maurizio Spadari, Yervant Zorian
    HD/sup 2/BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:892-901 [Conf]
  50. Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian
    HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1038-1044 [Conf]
  51. Francisco DaSilva, Yervant Zorian, Lee Whetsel, Karim Arabi, Rohit Kapur
    Overview of the IEEE P1500 Standard. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:988-997 [Conf]
  52. Cecil A. Dean, Yervant Zorian
    Do You Practice Safe Tests? What We Found Out About Your Habits. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:887-892 [Conf]
  53. Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
    An Effective BIST Scheme for Booth Multipliers. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:824-833 [Conf]
  54. Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
    An Effective BIST Scheme for Datapaths. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:76-85 [Conf]
  55. Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian, Mihalis Psarakis
    An Effective BIST Scheme for Arithmetic Logic Units. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:868-877 [Conf]
  56. Ilyoung Kim, Yervant Zorian, Goh Komoriya, Hai Pham, Frank P. Higgins, Jim L. Lewandowski
    Built in self repair for embedded high density SRAM. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:1112-1119 [Conf]
  57. Nektarios Kranitis, George Xenoulis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian
    Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:431-440 [Conf]
  58. Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik
    PSBIST: A Partial-Scan Based Built-In Self-Test Scheme. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:507-516 [Conf]
  59. Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian
    A distributed BIST technique for diagnosis of MCM interconnections. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:214-221 [Conf]
  60. Michel Renovell, Penelope Faure, Jean Michel Portal, Joan Figueras, Yervant Zorian
    IS-FPGA : a new symmetric FPGA architecture with implicit scan. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:924-931 [Conf]
  61. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    SRAM-based FPGA's: testing the LUT/RAM modules. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:1102-1111 [Conf]
  62. Michel Renovell, Yervant Zorian
    Different experiments in test generation for XILINX FPGAs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:854-862 [Conf]
  63. Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian
    Optimal Multiple Chain Relay Testing Scheme for MCMs on Large Area Substrates. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:818-827 [Conf]
  64. Harold N. Scholz, Duane R. Aadsen, Yervant Zorian
    A Method for Delay Fault Self-Testing of Macrocells. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:253-261 [Conf]
  65. Fabian Vargas, Michael Nicolaidis, Yervant Zorian
    An Approach for Designing Total-Dose Tolerant MCMs Based on Current Monitoring. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:345-354 [Conf]
  66. Yervant Zorian
    Embedded Memory Test and Repair: Infrastructure IP for SOC Yield. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:340-349 [Conf]
  67. Yervant Zorian
    Yield Threats and Inadequacy of One-time Test. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1284- [Conf]
  68. Yervant Zorian
    Investment vs. Yield Relationship for Memories in SOC. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1444- [Conf]
  69. Yervant Zorian
    Test Requirements for Embedded Core-Based Systems and IEEE P1500. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:191-199 [Conf]
  70. Yervant Zorian, Vinod K. Agarwal
    Higher Certainty of Error Coverage by Output Data Modification. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:140-147 [Conf]
  71. Yervant Zorian, A. J. van de Goor, Ivo Schanstra
    An Effective BIST Scheme for Ring-Address Type FIFOs. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:378-387 [Conf]
  72. Yervant Zorian, Erik Jan Marinissen, Sujit Dey
    Testing embedded-core based system chips. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:130-0 [Conf]
  73. Yervant Zorian, Erik Jan Marinissen, Rohit Kapur
    On using IEEE P1500 SECT for test plug-n-play. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:770-777 [Conf]
  74. Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel
    Towards a standard for embedded core test: an example. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:616-627 [Conf]
  75. Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel
    Wrapper design for embedded core test. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:911-920 [Conf]
  76. N. Derhacobian, Valery A. Vardanian, Yervant Zorian
    Embedded Memory Reliability: The SER Challenge. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:104-110 [Conf]
  77. Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
    An Approach for Evaluation of Redunancy Analysis Algorithms. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:51-0 [Conf]
  78. Valery A. Vardanian, Yervant Zorian
    A March-Based Fault Location Algorithm for Static Random Access Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:62-67 [Conf]
  79. Yervant Zorian
    Optimizing SoC Manufacturability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:37-38 [Conf]
  80. Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian
    Power Dissipation During Testing: Should We Worry About it? [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:456-457 [Conf]
  81. J. Borel, M. Cecchini, C. Malipeddi, Janusz Rajski, Yervant Zorian
    Systems On Silicon: Design and Test Challenges. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:184-185 [Conf]
  82. Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian
    Low Power/Energy BIST Scheme for Datapaths. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:23-28 [Conf]
  83. Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian
    Minimal March Tests for Unlinked Static Faults in Random Access Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:53-59 [Conf]
  84. Gurgen Harutunyan, Valery A. Vardanian, Y. Zorian Zorian
    Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:120-127 [Conf]
  85. Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian
    Instruction-Based Self-Testing of Processor Cores. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:223-228 [Conf]
  86. Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian
    A Test Interface for Built-In Test of Non-Isolated Scanned Cores. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:371-378 [Conf]
  87. Irith Pomeranz, Yervant Zorian
    Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:41-48 [Conf]
  88. Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
    Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:152-157 [Conf]
  89. Mihalis Psarakis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian
    An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:252-259 [Conf]
  90. Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian
    Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:15-21 [Conf]
  91. Michel Renovell, Joan Figueras, Yervant Zorian
    Test of RAM-based FPGA: methodology and application to the interconnect. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:230-237 [Conf]
  92. Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
    A Methodology for Design and Evaluation of Redundancy Allocation Algorithms. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:249-260 [Conf]
  93. Baosheng Wang, Yuejian Wu, Josh Yang, André Ivanov, Yervant Zorian
    SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:66-71 [Conf]
  94. Baosheng Wang, Josh Yang, James Cicalo, André Ivanov, Yervant Zorian
    Reducing Embedded SRAM Test Time under Redundancy Constraints. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:237-242 [Conf]
  95. Yervant Zorian, Dennis Wassung
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:154-155 [Conf]
  96. Yervant Zorian, Bruce C. Kim
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:334-335 [Conf]
  97. Alan Allan, Don Edenfeld, William H. Joyner Jr., Andrew B. Kahng, Mike Rodgers, Yervant Zorian
    2001 Technology Roadmap for Semiconductors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:1, pp:42-53 [Journal]
  98. Don Edenfeld, Andrew B. Kahng, Mike Rodgers, Yervant Zorian
    2003 Technology Roadmap for Semiconductors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:1, pp:47-56 [Journal]
  99. Yervant Zorian
    Nanoscale Design & Test Challenges. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2005, v:38, n:2, pp:36-39 [Journal]
  100. Yervant Zorian, Erik Jan Marinissen, Sujit Dey
    Testing Embedded-Core-Based System Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1999, v:32, n:6, pp:52-60 [Journal]
  101. Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian
    A Hierarchical Infrastructure for SoC Test Management. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:4, pp:32-39 [Journal]
  102. Dilip K. Bhavsar, Yervant Zorian
    ITC 97 Panel Sessions. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:7- [Journal]
  103. Meh-Ron Amerian, William D. Atwell Jr., Ian Burgess, Gary D. Fleeman, David Y. Lepejian, T. W. Williams, Farzad Zarrinfar, Yervant Zorian
    A D&T Roundtable: Testing Mixed Logic and DRAM Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:2, pp:86-92 [Journal]
  104. Juan Antonio Carballo, Yervant Zorian, Raul Camposano, Andrzej J. Strojwas, John Kibarian, Dennis Wassung, Alex Alexanian, Steve Wigley, Neil Kelly
    Guest Editors' Introduction: DFM Drives Changes in Design Flow. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:3, pp:200-205 [Journal]
  105. Sreejit Chakravarty, Ramalingam Sridhar, Shambhu J. Upadhyaya, Yervant Zorian, Gil Philips, Bozena Kaminska, Bernard Courtois
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:4, pp:95-97 [Journal]
  106. Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian
    Design & Test Education in Asia. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:4, pp:331-338 [Journal]
  107. Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
    Effective Built-In Self-Test for Booth Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:3, pp:105-111 [Journal]
  108. Rajesh K. Gupta, Yervant Zorian
    Introducing Core-Based System Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:4, pp:15-25 [Journal]
  109. Bruce C. Kim, Yervant Zorian
    Guest Editors' Introduction: Big Innovations in Small Packages. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:3, pp:186-187 [Journal]
  110. Nektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Mihalis Psarakis, Yervant Zorian
    Power-/Energy Efficient BIST Schemes for Processor Data Paths. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:15-28 [Journal]
  111. Gil Philips, Yervant Zorian, Charles W. Rosenthal, Bozena Kaminska
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:3, pp:8-144 [Journal]
  112. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    Testing the Interconnect of RAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:45-50 [Journal]
  113. Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
    SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:200-207 [Journal]
  114. Kenneth D. Wagner, Yervant Zorian
    EIC Message. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:2-0 [Journal]
  115. Yervant Zorian
    Flexibility and Programmability. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:1, pp:3-0 [Journal]
  116. Yervant Zorian
    Embedded in this issue. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:5-6 [Journal]
  117. Yervant Zorian
    Wider Coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:3, pp:6-0 [Journal]
  118. Yervant Zorian
    Huge Storage Capacity. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:3, pp:1-0 [Journal]
  119. Yervant Zorian
    Error-Free Products. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:4, pp:2-0 [Journal]
  120. Yervant Zorian
    EIC Message. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:5, pp:1-0 [Journal]
  121. Yervant Zorian
    Guest Editor's Introduction: Advances in Infrastructure IP. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:3, pp:49-0 [Journal]
  122. Yervant Zorian
    IEEE CASS becomes D&T Copublisher. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:3, pp:108-0 [Journal]
  123. Yervant Zorian
    D&T: 15th Year in Service. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:1-0 [Journal]
  124. Yervant Zorian
    Once Again, a Super Issue. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:3, pp:3-0 [Journal]
  125. Yervant Zorian
    Challenges and Options. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:4, pp:3-0 [Journal]
  126. Yervant Zorian
    Focus on DRAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:1, pp:1-0 [Journal]
  127. Yervant Zorian
    D&T Expands. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:3, pp:6-7 [Journal]
  128. Yervant Zorian
    Integration Continues. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:4, pp:1-0 [Journal]
  129. Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov
    Panel Summaries. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:3, pp:6-112 [Journal]
  130. Yervant Zorian, Rajesh K. Gupta
    Design and Test of Core-Based Systems on Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:4, pp:14-0 [Journal]
  131. Yervant Zorian, Dimitris Gizopoulos, Cary Vandenberg, Philippe Magarshack
    Guest Editors' Introduction: Design for Yield and Reliability. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:177-182 [Journal]
  132. Yervant Zorian, Jan Hlavicka
    Guest Editors' Introduction: East Meets West. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:1, pp:5-7 [Journal]
  133. Yervant Zorian, Samvel K. Shoukourian
    Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:3, pp:58-66 [Journal]
  134. Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
    An Effective Built-In Self-Test Scheme for Parallel Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:9, pp:936-950 [Journal]
  135. André Ivanov, Barry K. Tsuji, Yervant Zorian
    Programmable BIST Space Compactors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:12, pp:1393-1404 [Journal]
  136. Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
    Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:10, pp:1083-1099 [Journal]
  137. Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian
    Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:10, pp:1007-1019 [Journal]
  138. Yervant Zorian, André Ivanov
    An Effective BIST Scheme for ROM's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:5, pp:646-653 [Journal]
  139. André Ivanov, Yervant Zorian
    Count-based BIST compaction schemes and aliasing probability computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:768-777 [Journal]
  140. Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian
    Switching activity generation with automated BIST synthesis forperformance testing of interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1143-1158 [Journal]
  141. Irith Pomeranz, Yervant Zorian
    Fault isolation for nonisolated blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1385-1388 [Journal]
  142. Srikanth Venkataraman, Ruchir Puri, Steve Griffith, Ankush Oberai, Robert Madge, Greg Yeric, Walter Ng, Yervant Zorian
    Making Manufacturing Work For You. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:107-108 [Conf]
  143. Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian
    Minimal March Tests for Dynamic Faults in Random Access Memories. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:43-48 [Conf]
  144. Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian
    Minimal March Tests for Detection of Dynamic Faults in Random Access Memories. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:1, pp:55-74 [Journal]

  145. DFM: don't care or competitive weapon? [Citation Graph (, )][DBLP]


  146. Fault-secure shifter design: results and implementations. [Citation Graph (, )][DBLP]


  147. On the generation of pseudo-deterministic two-patterns test sequence with LFSRs. [Citation Graph (, )][DBLP]


  148. Panel Session - Vertical integration versus disaggregation. [Citation Graph (, )][DBLP]


  149. An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories. [Citation Graph (, )][DBLP]


  150. Guest Editors' Introduction: The Status of IEEE Std 1500. [Citation Graph (, )][DBLP]


  151. Guest Editor's Introduction: Examples of Management Decision Criteria. [Citation Graph (, )][DBLP]


  152. IEEE Std 1500 Enables Modular SoC Testing. [Citation Graph (, )][DBLP]


  153. Guest Editors' Introduction: The Status of IEEE Std 1500 - Part 2. [Citation Graph (, )][DBLP]


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