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Publications of Author

1. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
   Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2003, pp:250-255 [Conf]
   
2. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
   Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2004, pp:266-271 [Conf]
   
3. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
   Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:857-862 [Conf]
   
4. Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard
   Minimizing test power in SRAM through reduction of pre-charge activity. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:1159-1164 [Conf]
   
5. Luigi Dilillo, Bashir M. Al-Hashimi
   March CRF: an Efficient Test for Complex Read Faults in SRAM Memories. [Citation Graph (0, 0)][DBLP]
   DDECS, 2007, pp:173-178 [Conf]
   
6. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
   March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. [Citation Graph (0, 0)][DBLP]
   DDECS, 2006, pp:256-261 [Conf]
   
7. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
   March iC-: An Improved Version of March C- for ADOFs Detection. [Citation Graph (0, 0)][DBLP]
   VTS, 2004, pp:129-138 [Conf]
   
8. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan
   Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. [Citation Graph (0, 0)][DBLP]
   VTS, 2005, pp:183-188 [Conf]
   
9. Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard
   Reducing Power Dissipation in SRAM during Test. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:2, pp:271-280 [Journal]
   
10. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
    Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:5, pp:551-561 [Journal]
    
11. Simone Borri, Magali Bastian Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
    Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:2, pp:169-179 [Journal]
    
12. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
    ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:3, pp:287-296 [Journal]
    
13. 
    Delay Fault Diagnosis in Sequential Circuits. [Citation Graph (, )][DBLP]
    
    
14. 
    A statistical simulation method for reliability analysis of SRAM core-cells. [Citation Graph (, )][DBLP]
    
    
15. 
    A new design-for-test technique for SRAM core-cell stability faults. [Citation Graph (, )][DBLP]
    
    
16. 
    Comprehensive bridging fault diagnosis based on the SLAT paradigm. [Citation Graph (, )][DBLP]
    
    
17. 
    Impact of Resistive-Bridging Defects in SRAM Core-Cell. [Citation Graph (, )][DBLP]
    
    
18. 
    Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. [Citation Graph (, )][DBLP]
    
    
19. 
    Setting test conditions for improving SRAM reliability. [Citation Graph (, )][DBLP]
    
    
20. 
    A two-layer SPICE model of the ATMEL TSTAC^TM eFlash memory technology for defect injection and faulty behavior prediction. [Citation Graph (, )][DBLP]