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Arnaud Virazel:
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Publications of Author
- Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2003, pp:250-255 [Conf]
- Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2004, pp:266-271 [Conf]
- Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel
A BIST Structure to Test Delay Faults in a Scan Environment. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 1998, pp:435-439 [Conf]
- Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. [Citation Graph (0, 0)][DBLP] DAC, 2005, pp:857-862 [Conf]
- Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Design of Routing-Constrained Low Power Scan Chains. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:62-67 [Conf]
- Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. [Citation Graph (0, 0)][DBLP] DDECS, 2006, pp:256-261 [Conf]
- Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
A Mixed Approach for Unified Logic Diagnosis. [Citation Graph (0, 0)][DBLP] DDECS, 2007, pp:239-242 [Conf]
- Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Design of Routing-Constrained Low Power Scan Chains. [Citation Graph (0, 0)][DBLP] DELTA, 2004, pp:287-294 [Conf]
- René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Random Adjacent Sequences: An Efficient Solution for Logic BIST. [Citation Graph (0, 0)][DBLP] VLSI-SOC, 2001, pp:413-424 [Conf]
- Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. [Citation Graph (0, 0)][DBLP] IOLTW, 2000, pp:121-126 [Conf]
- Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault
Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. [Citation Graph (0, 0)][DBLP] PATMOS, 2005, pp:540-549 [Conf]
- O. Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
An Overview of Failure Mechanisms in Embedded Flash Memories. [Citation Graph (0, 0)][DBLP] VTS, 2006, pp:108-113 [Conf]
- René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
On Using Efficient Test Sequences for BIST. [Citation Graph (0, 0)][DBLP] VTS, 2002, pp:145-152 [Conf]
- Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
March iC-: An Improved Version of March C- for ADOFs Detection. [Citation Graph (0, 0)][DBLP] VTS, 2004, pp:129-138 [Conf]
- Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. [Citation Graph (0, 0)][DBLP] VTS, 2005, pp:183-188 [Conf]
- O. Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. [Citation Graph (0, 0)][DBLP] VTS, 2007, pp:47-52 [Conf]
- A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. [Citation Graph (0, 0)][DBLP] VTS, 2007, pp:361-368 [Conf]
- Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich
High Defect Coverage with Low-Power Test Sequences in a BIST Environment. [Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 2002, v:19, n:5, pp:44-52 [Journal]
- A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
Slow write driver faults in 65nm SRAM technology: analysis and March test solution. [Citation Graph (0, 0)][DBLP] DATE, 2007, pp:528-533 [Conf]
- Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. [Citation Graph (0, 0)][DBLP] VLSI-SoC, 2006, pp:403-408 [Conf]
- Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault
Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. [Citation Graph (0, 0)][DBLP] VLSI-SoC, 2005, pp:267-281 [Conf]
- Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
DERRIC: A Tool for Unified Logic Diagnosis. [Citation Graph (0, 0)][DBLP] European Test Symposium, 2007, pp:13-20 [Conf]
- O. Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. [Citation Graph (0, 0)][DBLP] European Test Symposium, 2007, pp:77-84 [Conf]
- A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. [Citation Graph (0, 0)][DBLP] European Test Symposium, 2007, pp:97-104 [Conf]
- Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2005, v:21, n:5, pp:551-561 [Journal]
- Simone Borri, Magali Bastian Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2005, v:21, n:2, pp:169-179 [Journal]
- Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
A Gated Clock Scheme for Low Power Testing of Logic Cores. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2006, v:22, n:1, pp:89-99 [Journal]
- Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2006, v:22, n:3, pp:287-296 [Journal]
Delay Fault Diagnosis in Sequential Circuits. [Citation Graph (, )][DBLP]
A statistical simulation method for reliability analysis of SRAM core-cells. [Citation Graph (, )][DBLP]
A Design-for-Diagnosis Technique for SRAM Write Drivers. [Citation Graph (, )][DBLP]
A new design-for-test technique for SRAM core-cell stability faults. [Citation Graph (, )][DBLP]
Comprehensive bridging fault diagnosis based on the SLAT paradigm. [Citation Graph (, )][DBLP]
Improving Diagnosis Resolution without Physical Information. [Citation Graph (, )][DBLP]
Impact of Resistive-Bridging Defects in SRAM Core-Cell. [Citation Graph (, )][DBLP]
Using TMR Architectures for Yield Improvement. [Citation Graph (, )][DBLP]
Yield Improvement, Fault-Tolerance to the Rescue?. [Citation Graph (, )][DBLP]
A case study on logic diagnosis for System-on-Chip. [Citation Graph (, )][DBLP]
An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. [Citation Graph (, )][DBLP]
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. [Citation Graph (, )][DBLP]
Setting test conditions for improving SRAM reliability. [Citation Graph (, )][DBLP]
A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction. [Citation Graph (, )][DBLP]
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