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M. Ray Mercer: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer
    On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:151-0 [Conf]
  2. Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer
    Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:354-359 [Conf]
  3. Kenneth M. Butler, M. Ray Mercer
    The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:673-678 [Conf]
  4. Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer
    Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:417-420 [Conf]
  5. Rhonda Kay Gaede, Don E. Ross, M. Ray Mercer, Kenneth M. Butler
    CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:597-600 [Conf]
  6. C. Thomas Glover, M. Ray Mercer
    A Method of Delay Fault Test Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:90-95 [Conf]
  7. C. Thomas Glover, M. Ray Mercer
    A Deterministic Approach to Adjacency Testing for Delay Faults. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:351-356 [Conf]
  8. Tom E. Kirkland, M. Ray Mercer
    A Topological Search Algorithm for ATPG. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:502-508 [Conf]
  9. Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
    Enhancing test efficiency for delay fault testing using multiple-clocked schemes. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:371-374 [Conf]
  10. M. Ray Mercer, Rohit Kapur, Don E. Ross
    Functional Approaches to Generating Orderings for Efficient Symbolic Representations. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:624-627 [Conf]
  11. Eun Sei Park, M. Ray Mercer
    An Efficient Delay Test Generation System for Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:522-528 [Conf]
  12. Steven P. Smith, M. Ray Mercer, B. Brodk
    Demand Driven Simulation: BACKSIM. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:181-187 [Conf]
  13. Thomas W. Williams, Bill Underwood, M. Ray Mercer
    The Interdependence Between Delay-Optimization of Synthesized Networks and Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:87-92 [Conf]
  14. Eric Schell, M. Ray Mercer
    CADTOOLS: a CAD algorithm development system. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:658-666 [Conf]
  15. Jennifer Dworak, Brad Cobb, James Wingfield, M. Ray Mercer
    Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1066-1071 [Conf]
  16. Rohit Kapur, Thomas W. Williams, M. Ray Mercer
    Directed-Binary Search in Logic BIST Diagnostics. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1121- [Conf]
  17. Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael R. Grimaila, M. Ray Mercer
    A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:94-101 [Conf]
  18. Jennifer Dworak, James Wingfield, Brad Cobb, Sooryong Lee, Li-C. Wang, M. Ray Mercer
    Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:177-185 [Conf]
  19. Jennifer Dworak, James Wingfield, M. Ray Mercer
    A Preliminary Investigation of Observation Diversity for Enhancing Fortuitous Detection of Defects. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:460-468 [Conf]
  20. James Wingfield, Jennifer Dworak, M. Ray Mercer
    Function-Based Dynamic Compaction and its Impact on Test Set Sizes. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:167-174 [Conf]
  21. Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer
    Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:332-337 [Conf]
  22. Tom E. Kirkland, M. Ray Mercer
    A Two-Level Guidance Heuristic for ATPG. [Citation Graph (0, 0)][DBLP]
    FJCC, 1986, pp:841-846 [Conf]
  23. Ronn B. Brashear, Douglas R. Holberg, M. Ray Mercer, Lawrence T. Pillage
    ETA: electrical-level timing analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:258-262 [Conf]
  24. Mark A. Heap, William A. Rogers, M. Ray Mercer
    A Synthesis Algorithm for Two-Level XOR Based Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:459-463 [Conf]
  25. Ronald W. Mehler, M. Ray Mercer
    Multi-Level Logic Minimization through Fault Dictionary Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:315-318 [Conf]
  26. Jaehong Park, M. Ray Mercer
    An Efficient Symbolic Design Verification System. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:294-298 [Conf]
  27. Jaehong Park, M. Ray Mercer
    Using Functional Information and Strategy Switching in Sequential ATPG. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:254-260 [Conf]
  28. Li-C. Wang, M. Ray Mercer, Thomas W. Williams
    A Better ATPG Algorithm and Its Design Principles. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:248-253 [Conf]
  29. Vishwani D. Agrawal, M. Ray Mercer
    Testability Measures : What Do They Tell Us ? [Citation Graph (0, 0)][DBLP]
    ITC, 1982, pp:391-399 [Conf]
  30. Vishwani D. Agrawal, M. Ray Mercer
    Deterministic Versus Random Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:718- [Conf]
  31. Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer
    Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:930-939 [Conf]
  32. Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer
    Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1031-1037 [Conf]
  33. Rhonda Kay Gaede, M. Ray Mercer, Bill Underwood
    Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:498-505 [Conf]
  34. Ki Soo Hwang, M. Ray Mercer
    Informed Test Generation Guidance Using Partially Specified Fanout Constraints. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:113-120 [Conf]
  35. Rohit Kapur, Jaehong Park, M. Ray Mercer
    All Tests for a Fault Are Not Equally Valuable for Defect Detection. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:762-769 [Conf]
  36. Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
    Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:407-416 [Conf]
  37. M. Ray Mercer
    Testing Issues at the University of Texas. [Citation Graph (0, 0)][DBLP]
    ITC, 1983, pp:158-159 [Conf]
  38. M. Ray Mercer
    Logic Elements for Universally Testable Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:493-497 [Conf]
  39. M. Ray Mercer, Vishwani D. Agrawal, Carlos M. Roman
    Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation. [Citation Graph (0, 0)][DBLP]
    ITC, 1981, pp:561-565 [Conf]
  40. Eun Sei Park, M. Ray Mercer
    Switch-Level ATPG Using Constraint-Guided Line Justification. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:616-625 [Conf]
  41. Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer
    Delay Testing Quality in Timing-Optimized Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:897-905 [Conf]
  42. Eun Sei Park, Thomas W. Williams, M. Ray Mercer
    Statistical Delay Fault Coverage and Defect Level for Delay Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:492-499 [Conf]
  43. John Salick, Bill Underwood, M. Ray Mercer
    Built-In Self Test Input Generator for Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:115-125 [Conf]
  44. Steven P. Smith, Bill Underwood, M. Ray Mercer
    D^3FS: A Demand Driven Deductive Fault Simulator. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:582-592 [Conf]
  45. Bill Underwood, M. Ray Mercer
    Correlating Testability with Fault Detection. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:697-704 [Conf]
  46. Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir
    Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1041-1050 [Conf]
  47. Li-C. Wang, M. Ray Mercer, Thomas W. Williams
    On Efficiently and Reliably Achieving Low Defective Part Levels. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:616-625 [Conf]
  48. Li-C. Wang, M. Ray Mercer, Thomas W. Williams
    Using Target Faults To Detect Non-Tartget Defects. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:629-638 [Conf]
  49. Thomas W. Williams, R. H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly
    IDDQ Test: Sensitivity Analysis of Scaling. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:786-792 [Conf]
  50. Jennifer Dworak, David Dorsey, Amy Wang, M. Ray Mercer
    Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:9-15 [Conf]
  51. Michael R. Grimaila, Sooryong Lee, Jennifer Dworak, Kenneth M. Butler, Bret Stewart, Hari Balachandran, Bryan Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. Ray Mercer
    REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:268-274 [Conf]
  52. Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams
    On the decline of testing efficiency as fault coverage approaches 100%. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:74-83 [Conf]
  53. M. Ray Mercer
    Testing and Design Verification of Electronic Components. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1991, v:24, n:9, pp:107-108 [Journal]
  54. Jennifer Dworak, Jason D. Wicker, Sooryong Lee, Michael R. Grimaila, M. Ray Mercer, Kenneth M. Butler, Bret Stewart, Li-C. Wang
    Defect-Oriented Testing and Defective-Part-Level Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:1, pp:31-41 [Journal]
  55. M. Ray Mercer
    Guest Editorial: ITC 20th Anniversary. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1990, v:7, n:2, pp:2-3 [Journal]
  56. Mark A. Heap, M. Ray Mercer
    Least Upper Bounds an OBDD Sizes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:6, pp:764-767 [Journal]
  57. Rohit Kapur, M. Ray Mercer
    Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:12, pp:1580-1588 [Journal]
  58. Eun Sei Park, M. Ray Mercer, Thomas W. Williams
    The Total Delay Fault Model and Statistical Delay Fault Coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:6, pp:688-698 [Journal]
  59. Ki Soo Hwang, M. Ray Mercer
    Derivation and Refinement of Fan-Out Constraints to Generate Tests in Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:564-572 [Journal]
  60. Eun Sei Park, M. Ray Mercer
    An efficient delay test generation system for combinational logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:926-938 [Journal]
  61. Chanhee Oh, M. Ray Mercer
    Efficient logic-level timing analysis using constraint-guided critical path search. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:3, pp:346-355 [Journal]

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