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Erik Larsson: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Stina Edbom, Erik Larsson
    An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:254-257 [Conf]
  2. Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng
    Integrated Test Scheduling, Test Parallelization and TAMDesign. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:397-404 [Conf]
  3. Erik Larsson, Hideo Fujiwara
    Optimal System-on-Chip Test Scheduling. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:306-311 [Conf]
  4. Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
    SOC Test Scheduling with Test Set Sharing and Broadcasting. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:162-169 [Conf]
  5. Erik Larsson, Zebo Peng
    Test Scheduling and Scan-Chain Division under Power Constraint. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:259-264 [Conf]
  6. Julien Pouget, Erik Larsson, Zebo Peng
    SOC Test Time Minimization Under Multiple Constraints. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:312-317 [Conf]
  7. Erik Larsson, Zebo Peng
    An integrated system-on-chip test framework. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:138-144 [Conf]
  8. Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
    A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:61-66 [Conf]
  9. Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
    Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:385-392 [Conf]
  10. Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
    Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:403-411 [Conf]
  11. Erik Larsson, Zebo Peng, Gunnar Carlsson
    The Design and Optimization of SOC Test Solutions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:523-530 [Conf]
  12. Erik Larsson
    Integrating Core Selection in the SOC Test Solution Design-Flow. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1349-1358 [Conf]
  13. Erik Larsson, Zebo Peng
    A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1135-1144 [Conf]
  14. John Saul, Betsy Black, Erik Larsson
    Helpdesk.Drew.Edu: Home Growing a Helpdesk Solution Using Open-Source Technology. [Citation Graph (0, 0)][DBLP]
    SIGUCCS, 2000, pp:289-293 [Conf]
  15. Erik Larsson, Hideo Fujiwara
    Test Resource Partitioning and Optimization for SOC Designs. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:319-324 [Conf]
  16. Erik Larsson, Julien Pouget, Zebo Peng
    Defect-Aware SOC Test Scheduling. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:361-366 [Conf]
  17. Erik Larsson, Zebo Peng
    Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:227-239 [Journal]
  18. Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng
    Efficient test solutions for core-based designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:758-775 [Journal]
  19. Erik Larsson, Hideo Fujiwara
    System-on-chip test scheduling with reconfigurable core wrappers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:305-309 [Journal]
  20. Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
    Optimized integration of test compression and sharing for SOC testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:207-212 [Conf]
  21. Tobias Dubois, Erik Jan Marinissen, Mohamed Azimane, Paul Wielage, Erik Larsson, Clemens Wouters
    Test quality analysis and improvement for an embedded asynchronous FIFO. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:859-864 [Conf]
  22. Erik Larsson, Stina Edbom
    Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:221-244 [Conf]
  23. Erik Larsson, Mehdi Amirijoo, Daniel Karlsson, Petru Eles
    What impacts course evaluation? [Citation Graph (0, 0)][DBLP]
    ITiCSE, 2007, pp:333- [Conf]
  24. Erik Larsson, Julien Pouget, Zebo Peng
    Abort-on-Fail Based Test Scheduling. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:6, pp:651-658 [Journal]
  25. Julien Pouget, Erik Larsson, Zebo Peng
    Multiple-Constraint Driven System-on-Chip Test Time Optimization. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:6, pp:599-611 [Journal]

  26. An Architecture for Combined Test Data Compression and Abort-on-Fail Test. [Citation Graph (, )][DBLP]


  27. On Scan Chain Diagnosis for Intermittent Faults. [Citation Graph (, )][DBLP]


  28. Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns. [Citation Graph (, )][DBLP]


  29. A controller testability analysis and enhancement technique. [Citation Graph (, )][DBLP]


  30. Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips. [Citation Graph (, )][DBLP]


  31. Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. [Citation Graph (, )][DBLP]


  32. Estimating Error-probability and its Application for Optimizing Roll-back Recovery with Checkpointing. [Citation Graph (, )][DBLP]


  33. Energy-efficient redundant execution for chip multiprocessors. [Citation Graph (, )][DBLP]


  34. Graph theoretic approach for scan cell reordering to minimize peak shift power. [Citation Graph (, )][DBLP]


  35. A distributed architecture to check global properties for post-silicon debug. [Citation Graph (, )][DBLP]


  36. On Minimization of Peak Power for Scan Circuit during Test. [Citation Graph (, )][DBLP]


  37. Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. [Citation Graph (, )][DBLP]


  38. Student-oriented examination in a computer architecture course. [Citation Graph (, )][DBLP]


  39. HeliCis: a DNA motif discovery tool for colocalized motif pairs with periodic spacing. [Citation Graph (, )][DBLP]


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