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Kent L. Einspahr: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth
    Synthesis of Sequential Circuits with Clock Control to Improve Testability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:472-0 [Conf]
  2. Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal
    Improving Circuit Testability by Clock Control. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:288-293 [Conf]
  3. Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr
    Exploiting don't cares to enhance functional tests. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:538-546 [Conf]
  4. Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth
    Synthesis for Testability by Two-Clock Control. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:279-283 [Conf]
  5. Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr
    Design Verification and Functional Testing of FiniteState Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:189-195 [Conf]
  6. Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth
    A synthesis for testability scheme for finite state machines using clock control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1780-1792 [Journal]

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