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Aiman H. El-Maleh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait
    Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:378-385 [Conf]
  2. Aiman H. El-Maleh, Mark Kassab, Janusz Rajski
    A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:625-631 [Conf]
  3. Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly
    On Test Set Preservation of Retimed Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:176-182 [Conf]
  4. Sadiq M. Sait, Habib Youssef, Junaid A. Khan, Aiman H. El-Maleh
    Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:484-487 [Conf]
  5. Aiman H. El-Maleh, Khaled Al-Utaibi
    On efficient extraction of partially specified test sets for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:545-548 [Conf]
  6. Sadiq M. Sait, Aiman H. El-Maleh, Rush H. Al-Abuji
    Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:457-460 [Conf]
  7. Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji
    General iterative heuristics for VLSI multiobjective partitioning. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:497-500 [Conf]
  8. Aiman H. El-Maleh, Yahya E. Osais
    A retiming-based test pattern generator design for built-in self test of data path architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:550-553 [Conf]
  9. Aiman H. El-Maleh, Khaled Al-Utaibi
    An Efficient Test Relaxation Technique for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:179-185 [Conf]
  10. Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly
    Testability Implications of Performance-Driven Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:2, pp:32-39 [Journal]
  11. Aiman H. El-Maleh, Khaled Al-Utaibi
    An efficient test relaxation technique for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:933-940 [Journal]
  12. Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait
    Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2556-2564 [Journal]
  13. Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly
    Behavior and testability preservation under the retiming transformation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:5, pp:528-543 [Journal]
  14. Aiman H. El-Maleh, Janusz Rajski
    Delay-fault testability preservation of the concurrent decomposition and factorization transformations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:582-590 [Journal]
  15. Thomas E. Marchok, Aiman H. El-Maleh, Wojciech Maly, Janusz Rajski
    A complexity analysis of sequential ATPG. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:11, pp:1409-1423 [Journal]
  16. Aiman H. El-Maleh, Yahya E. Osais
    Test vector decomposition-based static compaction algorithms for combinational circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:430-459 [Journal]
  17. Aiman H. El-Maleh, Sadiq M. Sait, F. Nawaz Khan
    Finite state machine state assignment for area and power minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  18. Transistor-level based defect tolerance for reliable nanoelectronics. [Citation Graph (, )][DBLP]


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