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Jawar Singh:
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Publications of Author
A Triple-Mode Sigma-Delta Modulator Design for Wireless Standards. [Citation Graph (, )][DBLP]
Single Event Upset Detection and Correction. [Citation Graph (, )][DBLP]
Single ended 6T SRAM with isolated read-port for low-power embedded systems. [Citation Graph (, )][DBLP]
Fault Tolerant Reversible Finite Field Arithmetic Circuits. [Citation Graph (, )][DBLP]
A nano-CMOS process variation induced read failure tolerant SRAM cell. [Citation Graph (, )][DBLP]
Fault tolerant bit parallel finite field multipliers using LDPC codes. [Citation Graph (, )][DBLP]
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead. [Citation Graph (, )][DBLP]
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. [Citation Graph (, )][DBLP]
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. [Citation Graph (, )][DBLP]
Failure analysis for ultra low power nano-CMOS SRAM under process variations. [Citation Graph (, )][DBLP]
Pseudo parallel architecture for AES with error correction. [Citation Graph (, )][DBLP]
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