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Marie-Lise Flottes: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Marie-Lise Flottes, Christian Landrault, A. Petitqueux
    Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:404-0 [Conf]
  2. Marie-Lise Flottes, R. Pires, Bruno Rouzeyre
    Alleviating DFT Cost Using Testability Driven HLS. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:46-51 [Conf]
  3. Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre
    A Heuristic for Test Scheduling at System Level. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1124- [Conf]
  4. Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre
    An Arithmetic Structure for Test Data Horizontal Compression. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:428-435 [Conf]
  5. Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe
    Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:921-922 [Conf]
  6. David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre
    A secure scan design methodology. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1177-1178 [Conf]
  7. Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre
    Mutation Sampling Technique for the Generation of Structural Test Data. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1022-1023 [Conf]
  8. Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    A Novel Parity Bit Scheme for SBox in AES Circuits. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:267-271 [Conf]
  9. Yves Bertrand, Marie-Lise Flottes, Florence Azaïs, Serge Bernard, Laurent Latorre, Regis Lorival
    European Network for Test Education. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:230-234 [Conf]
  10. Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre
    On Using Test Vector Differences for Reducing Test Pin Numbers. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:275-280 [Conf]
  11. Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre
    Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:295-300 [Conf]
  12. Marie-Lise Flottes, Yves Bertrand, L. Balado, E. Lupon, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich
    Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:135-139 [Conf]
  13. Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre
    Automatic Synthesis of BISTed Data Paths From High Level Specification. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:591-598 [Conf]
  14. Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre
    Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:401-412 [Conf]
  15. David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell
    Scan Design and Secure Chip. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:219-226 [Conf]
  16. David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre
    Secure Scan Techniques: A Comparison. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:119-124 [Conf]
  17. David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre
    BISTing data paths at behavioral level. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:672-680 [Conf]
  18. Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre
    Is High-Level Test Synthesis Just Design for Test? [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:294- [Conf]
  19. Yves Bertrand, Florence Azaïs, Marie-Lise Flottes, Regis Lorival
    A Successful Distance-Learning Experience for IC Test Education. [Citation Graph (0, 0)][DBLP]
    MSE, 1999, pp:20-21 [Conf]
  20. Yves Bertrand, Marie-Lise Flottes, L. Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich, J.-P. Van der Heyden
    Test Engineering Education in Europe: the EuNICE-Test Project. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:85-86 [Conf]
  21. Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe
    Low Cost Partial Scan Design: A High Level Synthesis Approach. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:332-340 [Conf]
  22. Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:57-62 [Conf]
  23. Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    A Dependable Parallel Architecture for SBoxes. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:132-137 [Conf]
  24. Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre
    Mutation Sampling Technique for the Generation of Structural Test Data [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  25. Analyzing testability from behavioral to RT level. [Citation Graph (, )][DBLP]


  26. An Integrated Validation Environment for Differential Power Analysis. [Citation Graph (, )][DBLP]


  27. AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis. [Citation Graph (, )][DBLP]


  28. Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers. [Citation Graph (, )][DBLP]


  29. Fault modelling and fault equivalence in CMOS technology. [Citation Graph (, )][DBLP]


  30. Improving the Test of NoC-Based SoCs with Help of Compression Schemes. [Citation Graph (, )][DBLP]


  31. Test data compression and TAM design. [Citation Graph (, )][DBLP]


  32. Evaluation of concurrent error detection techniques on the Advanced Encryption Standard. [Citation Graph (, )][DBLP]


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