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Antonis M. Paschalis:
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Publications of Author
- Nikolaos Gaitanis, Panagiotis Kostarakis, Antonis M. Paschalis
Totally Self Checking reconfigurable duplication system with separate internal fault indication. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 1995, pp:316-321 [Conf]
- Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
An effective BIST scheme for carry-save and carry-propagate array multipliers. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 1995, pp:298-302 [Conf]
- Ioannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis
An efficient comparative concurrent Built-In Self-Test technique. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 1995, pp:309-315 [Conf]
- Antonis M. Paschalis, Dimitris Nikolos, Constantine Halatsis
Efficient Modular Design of TSC Checkers for M-out-of-2M Codes. [Citation Graph (0, 0)][DBLP] Aegean Workshop on Computing, 1986, pp:144-155 [Conf]
- Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi
Systematic software-based self-test for pipelined processors. [Citation Graph (0, 0)][DBLP] DAC, 2006, pp:393-398 [Conf]
- Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian
Effective Low Power BIST for Datapaths. [Citation Graph (0, 0)][DBLP] DATE, 2000, pp:757- [Conf]
- Nektarios Kranitis, A. Merentitis, N. Laoutaris, G. Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos, Constantin Halatsis
Optimal periodic testing of intermittent faults in embedded pipelined processor applications. [Citation Graph (0, 0)][DBLP] DATE, 2006, pp:65-70 [Conf]
- Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian
Effective Software Self-Test Methodology for Processor Cores. [Citation Graph (0, 0)][DBLP] DATE, 2002, pp:592-597 [Conf]
- Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
Low-Cost Software-Based Self-Testing of RISC Processor Cores. [Citation Graph (0, 0)][DBLP] DATE, 2003, pp:10714-10719 [Conf]
- Antonis M. Paschalis, Dimitris Gizopoulos
Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:578-583 [Conf]
- Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Yervant Zorian
Deterministic software-based self-testing of embedded processor cores. [Citation Graph (0, 0)][DBLP] DATE, 2001, pp:92-96 [Conf]
- Antonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian
An Effective BIST Architecture for Fast Multiplier Cores. [Citation Graph (0, 0)][DBLP] DATE, 1999, pp:117-121 [Conf]
- Miltiadis Hatzimihail, Mihalis Psarakis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis
Software-Based Self-Test for Pipelined Processors: A Case Study. [Citation Graph (0, 0)][DBLP] DFT, 2005, pp:535-543 [Conf]
- Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis
Accumulator-Based Weighted Pattern Generation. [Citation Graph (0, 0)][DBLP] IOLTS, 2005, pp:215-220 [Conf]
- George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis
Test Generation Methodology for High-Speed Floating Point Adders. [Citation Graph (0, 0)][DBLP] IOLTS, 2005, pp:227-232 [Conf]
- George Xenoulis, Dimitris Gizopoulos, Nektarios Kranitis, Antonis M. Paschalis
Low-Cost, On-Line Software-Based Self-Testing of Embedded Processor Cores. [Citation Graph (0, 0)][DBLP] IOLTS, 2003, pp:149-0 [Conf]
- P. Kenterlis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis
A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP] IOLTS, 2006, pp:235-241 [Conf]
- Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. [Citation Graph (0, 0)][DBLP] ISQED, 2001, pp:343-349 [Conf]
- Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
An Effective BIST Scheme for Booth Multipliers. [Citation Graph (0, 0)][DBLP] ITC, 1995, pp:824-833 [Conf]
- Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
An Effective BIST Scheme for Datapaths. [Citation Graph (0, 0)][DBLP] ITC, 1996, pp:76-85 [Conf]
- Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian, Mihalis Psarakis
An Effective BIST Scheme for Arithmetic Logic Units. [Citation Graph (0, 0)][DBLP] ITC, 1997, pp:868-877 [Conf]
- Nektarios Kranitis, George Xenoulis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian
Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores. [Citation Graph (0, 0)][DBLP] ITC, 2003, pp:431-440 [Conf]
- Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantinos Halatsis
R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique. [Citation Graph (0, 0)][DBLP] ITC, 1998, pp:918-925 [Conf]
- Nikolaos Gaitanis, Dimitris Gizopoulos, Antonis M. Paschalis, Panagiotis Kostarakis
An asynchronous totally self-checking two-rail code error indicator. [Citation Graph (0, 0)][DBLP] VTS, 1996, pp:151-156 [Conf]
- Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis
Testing combinational iterative logic arrays for realistic faults. [Citation Graph (0, 0)][DBLP] VTS, 1995, pp:35-41 [Conf]
- Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian
Low Power/Energy BIST Scheme for Datapaths. [Citation Graph (0, 0)][DBLP] VTS, 2000, pp:23-28 [Conf]
- Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis
Robust Sequential Fault Testing of Iterative Logic Arrays. [Citation Graph (0, 0)][DBLP] VTS, 1997, pp:238-244 [Conf]
- Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian
Instruction-Based Self-Testing of Processor Cores. [Citation Graph (0, 0)][DBLP] VTS, 2002, pp:223-228 [Conf]
- Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model. [Citation Graph (0, 0)][DBLP] VTS, 1998, pp:152-157 [Conf]
- Mihalis Psarakis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian
An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers. [Citation Graph (0, 0)][DBLP] VTS, 1999, pp:252-259 [Conf]
- Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian
Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. [Citation Graph (0, 0)][DBLP] VTS, 2001, pp:15-21 [Conf]
- Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
Effective Built-In Self-Test for Booth Multipliers. [Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 1998, v:15, n:3, pp:105-111 [Journal]
- Nektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Mihalis Psarakis, Yervant Zorian
Power-/Energy Efficient BIST Schemes for Processor Data Paths. [Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 2000, v:17, n:4, pp:15-28 [Journal]
- Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis
Testing CMOS combinational iterative logic arrays for realistic faults. [Citation Graph (0, 0)][DBLP] Integration, 1996, v:21, n:3, pp:209-228 [Journal]
- Vassilios V. Dimakopoulos, G. Sourtziotis, Antonis M. Paschalis, Dimitris Nikolos
On TSC Checkers for m-out-n Codes. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1995, v:44, n:8, pp:1055-1059 [Journal]
- Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
An Effective Built-In Self-Test Scheme for Parallel Multipliers. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1999, v:48, n:9, pp:936-950 [Journal]
- Th. Haniotakis, Antonis M. Paschalis, Dimitris Nikolos
Efficient Totally Self-Checking Checkers for a Class of Borden Codes. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1995, v:44, n:11, pp:1318-1322 [Journal]
- Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, George Xenoulis
Software-Based Self-Testing of Embedded Processors. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2005, v:54, n:4, pp:461-475 [Journal]
- Dimitris Nikolos, Antonis M. Paschalis, George Philokyprou
Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1988, v:37, n:7, pp:807-814 [Journal]
- Antonis M. Paschalis, Costas Efstathiou, Constantine Halatsis
An Efficient TSC 1-out-of-3 Code Checker. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1990, v:39, n:3, pp:407-411 [Journal]
- Antonis M. Paschalis, Dimitris Nikolos, Constantine Halatsis
Efficient Modular Design of TSC Checkers for M-out-of-2M Codes. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1988, v:37, n:3, pp:301-309 [Journal]
- Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2000, v:49, n:10, pp:1083-1099 [Journal]
- George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis
Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2006, v:55, n:11, pp:1449-1457 [Journal]
- Antonis M. Paschalis, Dimitris Gizopoulos
Effective software-based self-test strategies for on-line periodic testing of embedded processors. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:88-99 [Journal]
- Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis
Built-in sequential fault self-testing of array multipliers. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:449-460 [Journal]
- Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis
Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1079-1086 [Journal]
- A. Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis
A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs. [Citation Graph (0, 0)][DBLP] IOLTS, 2007, pp:271-276 [Conf]
- A. Merentitis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos
Selecting Power-Optimal SBST Routines for On-Line Processor Testing. [Citation Graph (0, 0)][DBLP] European Test Symposium, 2007, pp:111-116 [Conf]
- Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Constantin Halatsis
A concurrent built-in self-test architecture based on a self-testing RAM. [Citation Graph (0, 0)][DBLP] IEEE Transactions on Reliability, 2005, v:54, n:1, pp:69-78 [Journal]
- A. Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis
Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:971-975 [Journal]
Functional Self-Testing for Bus-Based Symmetric Multiprocessors. [Citation Graph (, )][DBLP]
A totally self-checking 1-out-of-3 code error indicator. [Citation Graph (, )][DBLP]
On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors. [Citation Graph (, )][DBLP]
An Input Vector Monitoring Concurrent BIST scheme exploiting . [Citation Graph (, )][DBLP]
Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors. [Citation Graph (, )][DBLP]
Hybrid-SBST Methodology for Efficient Testing of Processor Cores. [Citation Graph (, )][DBLP]
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