Search the dblp DataBase
Michael S. Hsiao :
[Publications ]
[Author Rank by year ]
[Co-authors ]
[Prefers ]
[Cites ]
[Cited by ]
Publications of Author
Ashish Giani , Shuo Sheng , Michael S. Hsiao , Vishwani D. Agrawal Compaction-based test generation using state and fault information. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2000, pp:159-164 [Conf ] Michael S. Hsiao , Srimat T. Chakradhar Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1998, pp:452-457 [Conf ] Manan Syal , Michael S. Hsiao , Suriyaprakash Natarajan , Sreejit Chakravarty Untestable Multi-Cycle Path Delay Faults in Industrial Designs. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2005, pp:194-201 [Conf ] Ruofan Xu , Michael S. Hsiao Embedded core testing using genetic algorithms. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2000, pp:254-259 [Conf ] Liang Zhang , Michael S. Hsiao , Indradeep Ghosh Automatic Design Validation Framework for HDL Descriptions via RTL ATPG. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2003, pp:148-153 [Conf ] Liang Zhang , Mukul R. Prasad , Michael S. Hsiao Interleaved Invariant Checking with Dynamic Abstraction. [Citation Graph (0, 0)][DBLP ] CHARME, 2005, pp:81-96 [Conf ] Weixin Wu , Michael S. Hsiao Mining global constraints for improving bounded sequential equivalence checking. [Citation Graph (0, 0)][DBLP ] DAC, 2006, pp:743-748 [Conf ] Shuo Sheng , Koichiro Takayama , Michael S. Hsiao Effective safety property checking using simulation-based sequential ATPG. [Citation Graph (0, 0)][DBLP ] DAC, 2002, pp:813-818 [Conf ] Vishnu C. Vimjam , Michael S. Hsiao Fast illegal state identification for improving SAT-based induction. [Citation Graph (0, 0)][DBLP ] DAC, 2006, pp:241-246 [Conf ] Liang Zhang , Mukul R. Prasad , Michael S. Hsiao , Thomas Sidle Dynamic abstraction using SAT-based BMC. [Citation Graph (0, 0)][DBLP ] DAC, 2005, pp:754-757 [Conf ] Kameshwar Chandrasekar , Michael S. Hsiao Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:1002-1007 [Conf ] Ashish Giani , Shuo Sheng , Michael S. Hsiao , Vishwani D. Agrawal Efficient spectral techniques for sequential ATPG. [Citation Graph (0, 0)][DBLP ] DATE, 2001, pp:204-208 [Conf ] Kabir Gulrajani , Michael S. Hsiao Multi-Node Static Logic Implications for Redundancy Identification. [Citation Graph (0, 0)][DBLP ] DATE, 2000, pp:729-0 [Conf ] Michael S. Hsiao Maximizing Impossibilities for Untestable Fault Identification. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:949-953 [Conf ] Michael S. Hsiao Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits. [Citation Graph (0, 0)][DBLP ] DATE, 1999, pp:175-0 [Conf ] Michael S. Hsiao , Srimat T. Chakradhar State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] DATE, 1998, pp:577-582 [Conf ] Bin Li , Michael S. Hsiao , Shuo Sheng A Novel SAT All-Solutions Solver for Efficient Preimage Computation. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:272-279 [Conf ] Shuo Sheng , Michael S. Hsiao Efficient Preimage Computation Using A Novel Success-Driven ATPG. [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:10822-10827 [Conf ] Manan Syal , Michael S. Hsiao A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification. [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:10316-10321 [Conf ] Shrirang M. Yardi , Michael S. Hsiao , Thomas L. Martin , Dong S. Ha Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:340-345 [Conf ] Xiao Liu , Michael S. Hsiao Constrained ATPG for Broadside Transition Testing. [Citation Graph (0, 0)][DBLP ] DFT, 2003, pp:175-0 [Conf ] Lei Fang , Michael S. Hsiao Bilateral Testing of Nano-scale Fault-tolerant Circuits. [Citation Graph (0, 0)][DBLP ] DFT, 2006, pp:309-317 [Conf ] Gurjeet S. Saund , Michael S. Hsiao , Janak H. Patel Partial Scan beyond Cycle Cutting. [Citation Graph (0, 0)][DBLP ] FTCS, 1997, pp:320-328 [Conf ] Kameshwar Chandrasekar , Michael S. Hsiao Forward image computation with backtracing ATPG and incremental state-set construction. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2005, pp:254-259 [Conf ] Ronald P. Lajaunie , Michael S. Hsiao An effective and efficient ATPG-based combinational equivalence checker. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2005, pp:248-253 [Conf ] Vishnu C. Vimjam , Manan Syal , Michael S. Hsiao Untestable fault identification through enhanced necessary value assignments. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2005, pp:176-181 [Conf ] Xiaoding Chen , Michael S. Hsiao Characteristic faults and spectral information for logic BIST. [Citation Graph (0, 0)][DBLP ] ICCAD, 2002, pp:294-298 [Conf ] Michael S. Hsiao A fast, accurate, and non-statistical method for fault coverage estimation. [Citation Graph (0, 0)][DBLP ] ICCAD, 1998, pp:155-161 [Conf ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel Effects of delay models on peak power estimation of VLSI sequential circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:45-51 [Conf ] Liang Zhang , Mukul R. Prasad , Michael S. Hsiao Incremental deductive & inductive reasoning for SAT-based bounded model checking. [Citation Graph (0, 0)][DBLP ] ICCAD, 2004, pp:502-509 [Conf ] Kameshwar Chandrasekar , Michael S. Hsiao State Set Management for SAT-based Unbounded Model Checking. [Citation Graph (0, 0)][DBLP ] ICCD, 2005, pp:585-590 [Conf ] Michael S. Hsiao , Janak H. Patel A new architectural-level fault simulation using propagation prediction of grouped fault-effects. [Citation Graph (0, 0)][DBLP ] ICCD, 1995, pp:628-0 [Conf ] Manan Syal , Rajat Arora , Michael S. Hsiao Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults. [Citation Graph (0, 0)][DBLP ] ICCD, 2005, pp:453-460 [Conf ] Shrirang M. Yardi , Karthik Channakeshava , Michael S. Hsiao , Thomas L. Martin , Dong S. Ha A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management. [Citation Graph (0, 0)][DBLP ] ICCD, 2005, pp:119-126 [Conf ] Xueqi Cheng , Michael S. Hsiao Region-level approximate computation reuse for power reduction in multimedia applications. [Citation Graph (0, 0)][DBLP ] ISLPED, 2005, pp:119-122 [Conf ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel K2: an estimator for peak sustainable power of VLSI circuits. [Citation Graph (0, 0)][DBLP ] ISLPED, 1997, pp:178-183 [Conf ] Chung-Hsing Hsu , Ulrich Kremer , Michael S. Hsiao Compiler-directed dynamic voltage/frequency scheduling for energy reduction in mircoprocessors. [Citation Graph (0, 0)][DBLP ] ISLPED, 2001, pp:275-278 [Conf ] Phillip Stanley-Marbell , Michael S. Hsiao Fast, flexible, cycle-accurate energy estimation. [Citation Graph (0, 0)][DBLP ] ISLPED, 2001, pp:141-146 [Conf ] Kameshwar Chandrasekar , Michael S. Hsiao Decision Selection and Learning for an All-Solutions ATPG Engine. [Citation Graph (0, 0)][DBLP ] ITC, 2004, pp:607-616 [Conf ] Puneet Gupta , Michael S. Hsiao High Quality ATPG for Delay Defects. [Citation Graph (0, 0)][DBLP ] ITC, 2003, pp:584-591 [Conf ] Puneet Gupta , Michael S. Hsiao ALAPTF: A new Transition Faultmodel and the ATPG Algorithm. [Citation Graph (0, 0)][DBLP ] ITC, 2004, pp:1053-1060 [Conf ] Xiao Liu , Michael S. Hsiao , Sreejit Chakravarty , Paul J. Thadikaran Techniques to Reduce Data Volume and Application Time for Transition Test. [Citation Graph (0, 0)][DBLP ] ITC, 2002, pp:983-992 [Conf ] Sandhyo Seshadri , Michael S. Hsiao An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniques. [Citation Graph (0, 0)][DBLP ] ITC, 1999, pp:858-867 [Conf ] Nandini Sridhar , Michael S. Hsiao On efficient error diagnosis of digital circuits. [Citation Graph (0, 0)][DBLP ] ITC, 2001, pp:678-687 [Conf ] Manan Syal , Michael S. Hsiao , Sreejit Chakravarty Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks. [Citation Graph (0, 0)][DBLP ] ITC, 2004, pp:1034-1043 [Conf ] Qingwei Wu , Michael S. Hsiao Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal. [Citation Graph (0, 0)][DBLP ] ITC, 2003, pp:281-289 [Conf ] Qingwei Wu , Michael S. Hsiao State Variable Extraction to Reduce Problem Complexity for ATPG and Design Validation. [Citation Graph (0, 0)][DBLP ] ITC, 2004, pp:820-829 [Conf ] Liang Zhang , Indradeep Ghosh , Michael S. Hsiao Efficient Sequential ATPG for Functional RTL Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 2003, pp:290-298 [Conf ] Mukul R. Prasad , Michael S. Hsiao , Jawahar Jain Improving Sequential ATPG Using SAT Methods. [Citation Graph (0, 0)][DBLP ] IWLS, 2002, pp:79-84 [Conf ] Yufeng Zhao , Michael S. Hsiao Reducing Power Consumption by Utilizing Retransmission in Short Range Wireless Network. [Citation Graph (0, 0)][DBLP ] LCN, 2002, pp:527-533 [Conf ] Matthew Arnold , Michael S. Hsiao , Ulrich Kremer , Barbara G. Ryder Instruction Scheduling in the Presence of Java's Runtime Exceptions. [Citation Graph (0, 0)][DBLP ] LCPC, 1999, pp:18-34 [Conf ] Chung-Hsing Hsu , Ulrich Kremer , Michael S. Hsiao Compiler-Directed Dynamic Frequency and Voltage Scheduling. [Citation Graph (0, 0)][DBLP ] PACS, 2000, pp:65-81 [Conf ] Phillip Stanley-Marbell , Michael S. Hsiao , Ulrich Kremer A Hardware Architecture for Dynamic Performance and Energy Adaptation. [Citation Graph (0, 0)][DBLP ] PACS, 2002, pp:33-52 [Conf ] Thomas L. Martin , Michael S. Hsiao , Dong S. Ha , Jayan Krishnaswami Denial-of-Service Attacks on Battery-powered Mobile Computers. [Citation Graph (0, 0)][DBLP ] PerCom, 2004, pp:309-318 [Conf ] Daniel C. Nash , Thomas L. Martin , Dong S. Ha , Michael S. Hsiao Towards an Intrusion Detection System for Battery Exhaustion Attacks on Mobile Computing Devices. [Citation Graph (0, 0)][DBLP ] PerCom Workshops, 2005, pp:141-145 [Conf ] Rajat Arora , Michael S. Hsiao Enhancing SAT-based Bounded Model Checking using Sequential Logic Implications. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2004, pp:784-787 [Conf ] Kameshwar Chandrasekar , Michael S. Hsiao Q-PREZ: QBF Evaluation Using Partition, Resolution and Elimination with ZBDDs. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2005, pp:189-194 [Conf ] Anand L. D'Souza , Michael S. Hsiao Error Diagnosis of Sequential Circuits Using Region-Based Mode. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2001, pp:103-0 [Conf ] Michael S. Hsiao , Gurjeet S. Saund , Elizabeth M. Rudnick , Janak H. Patel Partial Scan Selection Based on Dynamic Reachability and Observability Information. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1998, pp:174-180 [Conf ] Dilip Krishnaswamy , Michael S. Hsiao , Vikram Saxena , Elizabeth M. Rudnick , Janak H. Patel , Prithviraj Banerjee Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1997, pp:475-481 [Conf ] Nachiketh R. Potlapally , Michael S. Hsiao , Anand Raghunathan , Ganesh Lakshminarayana , Srimat T. Chakradhar Accurate Power Macro-modeling Techniques for Complex RTL Circuits. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2001, pp:235-241 [Conf ] Mukul R. Prasad , Michael S. Hsiao , Jawahar Jain Can SAT be used to Improve Sequential ATPG Methods? [Citation Graph (0, 0)][DBLP ] VLSI Design, 2004, pp:585-0 [Conf ] Sameer Sharma , Michael S. Hsiao Combination of Structural and State Analysis for Partial Scan. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2001, pp:134-0 [Conf ] Manan Syal , Michael S. Hsiao Untestable Fault Identification using Recurrence Relations and Impossible Value Assignments. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2004, pp:481-486 [Conf ] Vishnu C. Vimjam , Michael S. Hsiao Explicit Safety Property Strengthening in SAT-based Induction. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2007, pp:63-68 [Conf ] Xiaoding Chen , Michael S. Hsiao Energy-Efficient Logic BIST Based on State Correlation Analysis. [Citation Graph (0, 0)][DBLP ] VTS, 2003, pp:267-272 [Conf ] Ashish Giani , Shuo Sheng , Michael S. Hsiao , Vishwani D. Agrawal Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment. [Citation Graph (0, 0)][DBLP ] VTS, 2001, pp:163-168 [Conf ] Ganapathy Kasturirangan , Michael S. Hsiao Spectrum-Based BIST in Complex SOCs. [Citation Graph (0, 0)][DBLP ] VTS, 2002, pp:111-116 [Conf ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel Automatic test generation using genetically-engineered distinguishing sequences. [Citation Graph (0, 0)][DBLP ] VTS, 1996, pp:216-223 [Conf ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors. [Citation Graph (0, 0)][DBLP ] VTS, 1997, pp:188-195 [Conf ] Qingwei Wu , Michael S. Hsiao Efficient ATPG for Design Validation Based On Partitioned State Exploration Histories. [Citation Graph (0, 0)][DBLP ] VTS, 2004, pp:389-405 [Conf ] Ankur Jain , Vamsi Boppana , Rajarshi Mukherjee , Jawahar Jain , Masahiro Fujita , Michael S. Hsiao Testing, Verification, and Diagnosis in the Presence of Unknowns. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:263-270 [Conf ] Ankur Jain , Michael S. Hsiao , Vamsi Boppana , Masahiro Fujita On the Evaluation of Arbitrary Defect Coverage of Test Sets. [Citation Graph (0, 0)][DBLP ] VTS, 1999, pp:426-432 [Conf ] Sameer Sharma , Michael S. Hsiao Partial Scan Using Multi-Hop State Reachability Analysis. [Citation Graph (0, 0)][DBLP ] VTS, 1999, pp:121-127 [Conf ] Manan Syal , Michael S. Hsiao , Kiran B. Doreswamy , Sreejit Chakravarty Efficient Implication - Based Untestable Bridge Fault Identifier. [Citation Graph (0, 0)][DBLP ] VTS, 2003, pp:393-402 [Conf ] Vishnu C. Vimjam , Michael S. Hsiao Efficient Fault Collapsing via Generalized Dominance Relations. [Citation Graph (0, 0)][DBLP ] VTS, 2006, pp:258-265 [Conf ] Vishnu C. Vimjam , M. Enamul Amyeen , Ruifeng Guo , Srikanth Venkataraman , Michael S. Hsiao , Kai Yang Using Scan-Dump Values to Improve Functional-Diagnosis Methodology. [Citation Graph (0, 0)][DBLP ] VTS, 2007, pp:231-238 [Conf ] Xiao Liu , Michael S. Hsiao A Novel Transition Fault ATPG That Reduces Yield Loss. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2005, v:22, n:6, pp:576-584 [Journal ] Shuo Sheng , Michael S. Hsiao Efficient Sequential Test Generation Based on Logic Simulation. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2002, v:19, n:5, pp:56-64 [Journal ] Shuo Sheng , Michael S. Hsiao Success-Driven Learning in ATPG for Preimage Computation. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:504-512 [Journal ] Matthew Arnold , Michael S. Hsiao , Ulrich Kremer , Barbara G. Ryder Exploring the Interaction between Java?s Implicitly Thrown Exceptions and Instruction Scheduling. [Citation Graph (0, 0)][DBLP ] International Journal of Parallel Programming, 2001, v:29, n:2, pp:111-137 [Journal ] Rajat Arora , Michael S. Hsiao Using Global Structural Relationships of Signals to Accelerate SAT-based Combinational Equivalence Checking. [Citation Graph (0, 0)][DBLP ] J. UCS, 2004, v:10, n:12, pp:1597-1628 [Journal ] Xiaoding Chen , Michael S. Hsiao Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2006, v:55, n:2, pp:150-162 [Journal ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel Fast Static Compaction Algorithms for Sequential Circuit Test Vectors. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1999, v:48, n:3, pp:311-322 [Journal ] Qingwei Wu , Michael S. Hsiao A New Simulation-Based Property Checking Algorithm Based on Partitioned Alternative Search Space Traversal. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2006, v:55, n:11, pp:1325-1334 [Journal ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:239-254 [Journal ] Qingwei Wu , Michael S. Hsiao State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design Validation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2275-2282 [Journal ] Manan Syal , Michael S. Hsiao New techniques for untestable fault identification in sequential circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1117-1131 [Journal ] Liang Zhang , Indradeep Ghosh , Michael S. Hsiao A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2526-2538 [Journal ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel Dynamic state traversal for sequential circuit test generation. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:548-565 [Journal ] Xiao Liu , Michael S. Hsiao , Sreejit Chakravarty , Paul J. Thadikaran Efficient techniques for transition testing. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:2, pp:258-278 [Journal ] Lei Fang , Michael S. Hsiao A new hybrid solution to boost SAT solver performance. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1307-1313 [Conf ] Xiaoding Chen , Michael S. Hsiao An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:4, pp:404-412 [Journal ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel Peak power estimation of VLSI circuits: new peak power measures. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:435-439 [Journal ] Anand L. D'Souza , Michael S. Hsiao Error Diagnosis of Sequential Circuits Using Region-Based Model. [Citation Graph (0, 0)][DBLP ] J. Electronic Testing, 2005, v:21, n:2, pp:115-126 [Journal ] Using Non-trivial Logic Implications for Trace Buffer-Based Silicon Debug. [Citation Graph (, )][DBLP ] Kiss the Scan Goodbye: A Non-scan Architecture for High Coverage, Low Test Data Volume and Low Test Application Time. [Citation Graph (, )][DBLP ] On Providing Automatic Parental Consent over Information Collection from Children. [Citation Graph (, )][DBLP ] Efficient Design Validation Based on Cultural Algorithms. [Citation Graph (, )][DBLP ] A Fast Approximation Algorithm for MIN-ONE SAT. [Citation Graph (, )][DBLP ] Simulation-Directed Invariant Mining for Software Verification. [Citation Graph (, )][DBLP ] Sequential circuit test generation using dynamic state traversal. [Citation Graph (, )][DBLP ] An efficient path-oriented bitvector encoding width computation algorithm for bit-precise verification. [Citation Graph (, )][DBLP ] Reversible logic synthesis through ant colony optimization. [Citation Graph (, )][DBLP ] SAT-based equivalence checking of threshold logic designs for nanotechnologies. [Citation Graph (, )][DBLP ] Guided test generation for isolation and detection of embedded trojans in ics. [Citation Graph (, )][DBLP ] Bounded model checking of embedded software in wireless cognitive radio systems. [Citation Graph (, )][DBLP ] Implicit Search-Space Aware Cofactor Expansion: A Novel Preimage Computation Technique. [Citation Graph (, )][DBLP ] Quantifying the energy efficiency of coordinated micro-architectural adaptation for multimedia workloads. [Citation Graph (, )][DBLP ] Ant Colony Optimization directed program abstraction for software bounded model checking. [Citation Graph (, )][DBLP ] Multiplexed trace signal selection using non-trivial implication-based correlation. [Citation Graph (, )][DBLP ] Evaluation of Online Resources in Assisting Phishing Detection. [Citation Graph (, )][DBLP ] A Novel Sustained Vector Technique for the Detection of Hardware Trojans. [Citation Graph (, )][DBLP ] A Region Based Approach for the Identification of Hardware Trojans. [Citation Graph (, )][DBLP ] VITAMIN: Voltage Inversion Technique to Ascertain Malicious Insertions in ICs. [Citation Graph (, )][DBLP ] Search in 0.007secs, Finished in 0.559secs