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Publications of Author

1. Emil Gizdarski, Hideo Fujiwara
   Spirit: satisfiability problem implementation for redundancy identification and test generation. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2000, pp:171-178 [Conf]
   
2. Emil Gizdarski, Hideo Fujiwara
   Fault Set Partition for Efficient Width Compression. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2002, pp:194-199 [Conf]
   
3. Michiko Inoue, Emil Gizdarski, Hideo Fujiwara
   A class of sequential circuits with combinational test generation complexity under single-fault assumption. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2000, pp:398-403 [Conf]
   
4. Emil Gizdarski, Hideo Fujiwara
   A Framework for Low Complexity Static Learning. [Citation Graph (0, 0)][DBLP]
   DAC, 2001, pp:546-549 [Conf]
   
5. Davide Appello, Alessandra Fudoli, Katia Giarda, Emil Gizdarski, Ben Mathew, Vincenzo Tancorre
   Yield Analysis of Logic Circuits. [Citation Graph (0, 0)][DBLP]
   VTS, 2004, pp:103-108 [Conf]
   
6. Emil Gizdarski, Hideo Fujiwara
   SPIRIT: A Highly Robust Combinational Test Generation Algorithm. [Citation Graph (0, 0)][DBLP]
   VTS, 2001, pp:346-351 [Conf]
   
7. Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams
   A Reconfigurable Shared Scan-in Architecture. [Citation Graph (0, 0)][DBLP]
   VTS, 2003, pp:9-14 [Conf]
   
8. Nodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams
   Changing the Scan Enable during Shift. [Citation Graph (0, 0)][DBLP]
   VTS, 2004, pp:73-78 [Conf]
   
9. Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew
   Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST. [Citation Graph (0, 0)][DBLP]
   VTS, 2005, pp:359-365 [Conf]
   
10. Peter Wohl, John A. Waicukauski, Rohit Kapur, S. Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini
    Minimizing the Impact of Scan Compression. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:67-74 [Conf]
    
11. Davide Appello, Alessandra Fudoli, Katia Giarda, Vincenzo Tancorre, Emil Gizdarski, Ben Mathew
    Understanding Yield Losses in Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:208-215 [Journal]
    
12. Emil Gizdarski
    Built-in self-test for folded bit-line Mbit DRAMs. [Citation Graph (0, 0)][DBLP]
    Integration, 1996, v:21, n:1-2, pp:95-112 [Journal]
    
13. Emil Gizdarski, Hideo Fujiwara
    SPIRIT: a highly robust combinational test generation algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1446-1458 [Journal]
    
14. 
    Fully X-tolerant, very high scan compression. [Citation Graph (, )][DBLP]
    
    
15. 
    Constructing Augmented Multimode Compactors. [Citation Graph (, )][DBLP]
    
    
16. 
    Constructing augmented time compactors. [Citation Graph (, )][DBLP]