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Title:
Author:
Jacob Savir: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zhen Guo, Xi Min Zhang, Jacob Savir, Yun-Qing Shi
    On Test and Characterization of Analog Linear Time-Invariant Circuits Using Neural Networks. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:338-343 [Conf]
  2. Jacob Savir
    On testing safety-sensitive digital systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:478-483 [Conf]
  3. Jacob Savir
    Generator choices for delay test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:214-221 [Conf]
  4. Jacob Savir
    Module level weighted random patterns. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:274-278 [Conf]
  5. Jacob Savir
    On The Tradeoff Between Number of Clocks and Number of Latches in Shift Registers. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:296-299 [Conf]
  6. Jacob Savir
    On Chip Weighted Random Patterns. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:343-352 [Conf]
  7. Jacob Savir
    BIST Diagnostics, Part 1: Simulation Models. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:8-14 [Conf]
  8. Jacob Savir, Zhen Guo
    Test Limitations of Parametric Faults in Analog Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:39-44 [Conf]
  9. Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara
    Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:32-39 [Conf]
  10. Jacob Savir
    Why Partial Design Verification Works Better Than It Should. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:704-707 [Conf]
  11. Zhen Guo, Jacob Savir
    Observer-Based Test of Analog Linear Time-Invariant Circuits. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:13-17 [Conf]
  12. Jacob Savir
    Memory Chip BIST Architecture. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:384-0 [Conf]
  13. Jacob Savir
    BIST-Based Fault Diagnosis in the Presence of Embedded Memories. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:37-47 [Conf]
  14. Jacob Savir
    Design for Testability to Combat Delay Faults. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:407-411 [Conf]
  15. Jacob Savir, Zhen Guo
    On the Detectability of Parametric Faults in Analog Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:273-276 [Conf]
  16. Zeev Barzilai, Jacob Savir, George Markowsky, Merlin G. Smith
    VLSI Self-Testing Based on Syndrome Techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 1981, pp:102-109 [Conf]
  17. Zhen Guo, Jacob Savir
    Analog Circuit Test using Transfer Function Coe .cient Estimates. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1155-1163 [Conf]
  18. William H. McAnney, Jacob Savir
    Built-In Checking of the Correct Self-Test Signature. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:54-59 [Conf]
  19. Srinivas Patil, Jacob Savir
    Skewed-Load Transition Test: Part 2, Coverage. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:714-722 [Conf]
  20. Qiang Peng, Miron Abramovici, Jacob Savir
    MUST: multiple-stem analysis for identifying sequentially untestable faults. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:839-846 [Conf]
  21. Jacob Savir
    On-line and off-line test of airborne digital systems: a reliability study. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:35-44 [Conf]
  22. Jacob Savir
    Skewed-Load Transition Test: Part 1, Calculus. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:705-713 [Conf]
  23. Jacob Savir
    Scan Latch Design for Delay Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:446-453 [Conf]
  24. Jacob Savir, Paul H. Bardell
    On Random Pattern Test Length. [Citation Graph (0, 0)][DBLP]
    ITC, 1983, pp:95-107 [Conf]
  25. Jacob Savir, Robert F. Berry
    At-Speed Test is not Necessarily an AC Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:722-728 [Conf]
  26. Jacob Savir, William H. McAnney
    Random Pattern Testability of Delay Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:263-273 [Conf]
  27. Jacob Savir, William H. McAnney
    Identification of Failing Tests with Cycling Registers. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:322-328 [Conf]
  28. Jacob Savir, William H. McAnney, Salvatore R. Vecchio
    Random Pattern Testing for Data-Line Faults in an Embedded Multiport Memory. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:100-105 [Conf]
  29. Jacob Savir, William H. McAnney, Salvatore R. Vecchio
    Random Pattern Testing for Address-Line Faults in an Embedded Multiport Memory. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:106-114 [Conf]
  30. Jacob Savir, William H. McAnney, Salvatore R. Vecchio
    Testing for Coupled Cells in Random-Access Memories. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:439-451 [Conf]
  31. Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma
    Delay Fault Testing: How Robust are Our Models? [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:502-503 [Conf]
  32. Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara
    BIST Pretest of ICs: Risks and Benefits. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:142-149 [Conf]
  33. Jacob Savir
    On shrinking wide compressors. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:108-117 [Conf]
  34. Jacob Savir
    Random pattern testability of memory control logic. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:399-409 [Conf]
  35. Jacob Savir
    Salvaging test windows in BIST diagnostic. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:416-425 [Conf]
  36. Jacob Savir
    Distributed Generation of Weighted Random Patterns. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:225-233 [Conf]
  37. Zeev Barzilai, Jacob Savir, George Markowsky, Merlin G. Smith
    The Weighted Syndrome Sums Approach to VLSI Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:12, pp:996-1000 [Journal]
  38. A. Boneh, Jacob Savir
    Statistical Resistance to Detection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:1, pp:123-126 [Journal]
  39. William H. McAnney, Jacob Savir
    Built-In Checking of the Correct Self-Test Signature. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:9, pp:1142-1145 [Journal]
  40. Jacob Savir, Gary S. Ditlow, Paul H. Bardell
    Random Pattern Testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:1, pp:79-90 [Journal]
  41. Jacob Savir, William H. McAnney
    Random Pattern Testability of Delay Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:3, pp:291-300 [Journal]
  42. Jacob Savir, William H. McAnney
    A Multiple Seed Linear Feedback Shift Register. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:2, pp:250-252 [Journal]
  43. Jacob Savir, William H. McAnney, Salvatore R. Vecchio
    Fault Propagation Through Embedded Multiport Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:5, pp:592-602 [Journal]
  44. Jacob Savir, William H. McAnney, Salvatore R. Vecchio
    Testing for Coupled Cells in Random-Access Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:10, pp:1177-1180 [Journal]
  45. Jacob Savir
    Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:5, pp:410-416 [Journal]
  46. Jacob Savir
    Syndrome-Testable Design of Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:6, pp:442-451 [Journal]
  47. Jacob Savir
    Detection of Single Intermittent Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:7, pp:673-678 [Journal]
  48. Jacob Savir
    Syndrome-Testing of ``Syndrome-Untestable'' Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:8, pp:606-608 [Journal]
  49. Jacob Savir
    A New Empirical Test for the Quality of Random Integer Generators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:10, pp:960-961 [Journal]
  50. Jacob Savir
    Good Controllability and Observability Do Not Guarantee Good Testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:12, pp:1198-1200 [Journal]
  51. Jacob Savir
    The Bidirectional Double Latch (BDDL). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:1, pp:65-66 [Journal]
  52. Jacob Savir
    Reducing the MISR Size. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:8, pp:930-938 [Journal]
  53. Jacob Savir
    Random Pattern Testability of Memory Control Logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:3, pp:305-312 [Journal]
  54. Jacob Savir
    Salvaging Test Windows in BIST Diagnostics. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:4, pp:486-491 [Journal]
  55. Jacob Savir
    Distributed Generation of Weighted Random Patterns. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:12, pp:1364-1368 [Journal]
  56. Jacob Savir, Paul H. Bardell
    On Random Pattern Test Length. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:6, pp:467-474 [Journal]
  57. Thomas H. Spencer, Jacob Savir
    Layout Influences Testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:3, pp:287-290 [Journal]
  58. Jacob Savir
    Shrinking wide compressors [BIST]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1379-1387 [Journal]
  59. Jacob Savir
    Random pattern testability of memory address logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1310-1318 [Journal]
  60. Jacob Savir, Paul H. Bardell
    Partitioning of polynomial tasks: test generation, an example. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1465-1468 [Journal]
  61. Jacob Savir, Srinivas Patil
    Scan-based transition test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1232-1241 [Journal]
  62. Jacob Savir, Srinivas Patil
    Broad-side delay test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:1057-1064 [Journal]
  63. Jacob Savir, Srinivas Patil
    On broad-side delay test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:368-372 [Journal]
  64. Jacob Savir
    Redundancy revisited. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:620-624 [Journal]

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