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Anshuman Chandra: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra
    Rapid and Energy-Efficient Testing for Embedded Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:8-13 [Conf]
  2. Yinhe Han, Xiaowei Li, Shivakumar Swaminathan, Yu Hu, Anshuman Chandra
    Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:372-377 [Conf]
  3. Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra
    Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:440-445 [Conf]
  4. Anshuman Chandra, Krishnendu Chakrabarty
    Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:166-169 [Conf]
  5. Anshuman Chandra, Krishnendu Chakrabarty
    Reduction of SOC test data volume, scan power and testing time using alternating run-length codes. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:673-678 [Conf]
  6. Anshuman Chandra, Krishnendu Chakrabarty
    Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:145-149 [Conf]
  7. Anshuman Chandra, Krishnendu Chakrabarty
    Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:598-603 [Conf]
  8. Vikram Iyengar, Anshuman Chandra, Sharon Schweizer, Krishnendu Chakrabarty
    A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11188-11190 [Conf]
  9. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra
    Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:298-305 [Conf]
  10. Vikram Iyengar, Anshuman Chandra
    A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:511-518 [Conf]
  11. Anshuman Chandra, Krishnendu Chakrabarty
    Test Data Compression for System-on-a-Chip Using Golomb Codes. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:113-120 [Conf]
  12. Anshuman Chandra, Krishnendu Chakrabarty
    Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:42-47 [Conf]
  13. Anshuman Chandra, Krishnendu Chakrabarty, Rafael A. Medina
    How Effective are Compression Codes for Reducing Test Data Volume? [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:91-96 [Conf]
  14. Anshuman Chandra, Haihua Yan, Rohit Kapur
    Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:84-92 [Conf]
  15. Anshuman Chandra, Krishnendu Chakrabarty
    Test Resource Partitioning for SOCs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:5, pp:80-91 [Journal]
  16. Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra
    Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:201-209 [Journal]
  17. Anshuman Chandra, Krishnendu Chakrabarty
    Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:8, pp:1076-1088 [Journal]
  18. Anshuman Chandra, Krishnendu Chakrabarty
    System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:3, pp:355-368 [Journal]
  19. Anshuman Chandra, Krishnendu Chakrabarty
    Low-power scan testing and test data compression forsystem-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:597-604 [Journal]
  20. Anshuman Chandra, Krishnendu Chakrabarty
    Test data compression and decompression based on internal scanchains and Golomb coding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:715-722 [Journal]
  21. Anshuman Chandra, Krishnendu Chakrabarty
    A unified approach to reduce SOC test data volume, scan power and testing time. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:352-363 [Journal]
  22. Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra
    Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:531-540 [Journal]

  23. Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction. [Citation Graph (, )][DBLP]


  24. Scalable Adaptive Scan (SAS). [Citation Graph (, )][DBLP]


  25. Interval Based X-Masking for Scan Compression Architectures. [Citation Graph (, )][DBLP]


  26. Proactive management of X's in scan chains for compression. [Citation Graph (, )][DBLP]


  27. Bounded Adjacent Fill for Low Capture Power Scan Testing. [Citation Graph (, )][DBLP]


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