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Janak H. Patel :
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John W. C. Fu , Janak H. Patel Data Prefetching in Multiprocessor Vector Cache Memories. [Citation Graph (1, 0)][DBLP ] ISCA, 1991, pp:54-63 [Conf ] David W. L. Yen , Janak H. Patel , Edward S. Davidson Memory Interference in Synchronous Multiprocessor Systems. [Citation Graph (1, 0)][DBLP ] IEEE Trans. Computers, 1982, v:31, n:11, pp:1116-1121 [Journal ] Eiji Harada , Janak H. Patel Overhead reduction techniques for hierarchical fault simulation. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1995, pp:79-85 [Conf ] Jacob A. Abraham , Sandip Kundu , Janak H. Patel , Manuel A. d'Abreu , Bulent I. Dervisoglu , Marc E. Levitt , Hector R. Sucar , Ron G. Walther Microprocessor Testing: Which Technique is Best? (Panel). [Citation Graph (0, 0)][DBLP ] DAC, 1994, pp:294- [Conf ] Susheel J. Chandra , Janak H. Patel A Hierarchical Approach Test Vector Generation. [Citation Graph (0, 0)][DBLP ] DAC, 1987, pp:495-501 [Conf ] Vivek Chickermane , Elizabeth M. Rudnick , Prithviraj Banerjee , Janak H. Patel Non-Scan Design-for-Testability Techniques for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] DAC, 1993, pp:236-241 [Conf ] U. J. Davé , Janak H. Patel A Functional-Level Test Generation Methodology Using Two-level Representations. [Citation Graph (0, 0)][DBLP ] DAC, 1989, pp:722-725 [Conf ] SungHo Kim , Prithviraj Banerjee , Vivek Chickermane , Janak H. Patel APT: An Area-Performance-Testability Driven Placement Algorithm. [Citation Graph (0, 0)][DBLP ] DAC, 1992, pp:141-146 [Conf ] Jaushin Lee , Janak H. Patel Hierarchical Test Generation under Intensive Global Functional Constraints. [Citation Graph (0, 0)][DBLP ] DAC, 1992, pp:261-266 [Conf ] Pinaki Mazumder , Janak H. Patel , W. Kent Fuchs Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories. [Citation Graph (0, 0)][DBLP ] DAC, 1987, pp:689-694 [Conf ] Thomas M. Niermann , Wu-Tung Cheng , Janak H. Patel Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator. [Citation Graph (0, 0)][DBLP ] DAC, 1990, pp:535-540 [Conf ] Steven Parkes , Prithviraj Banerjee , Janak H. Patel ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation. [Citation Graph (0, 0)][DBLP ] DAC, 1994, pp:717-721 [Conf ] Sanjay J. Patel , Janak H. Patel Effectiveness of heuristics measures for automatic test pattern generation. [Citation Graph (0, 0)][DBLP ] DAC, 1986, pp:547-552 [Conf ] Srinivas Patil , Prithviraj Banerjee , Janak H. Patel Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors. [Citation Graph (0, 0)][DBLP ] DAC, 1991, pp:155-159 [Conf ] Elizabeth M. Rudnick , Janak H. Patel Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP ] DAC, 1995, pp:183-188 [Conf ] Elizabeth M. Rudnick , Janak H. Patel , Gary S. Greenstein , Thomas M. Niermann Sequential Circuit Test Generation in a Genetic Algorithm Framework. [Citation Graph (0, 0)][DBLP ] DAC, 1994, pp:698-704 [Conf ] Srikanth Venkataraman , Ismed Hartanto , W. Kent Fuchs , Elizabeth M. Rudnick , Sreejit Chakravarty , Janak H. Patel Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. [Citation Graph (0, 0)][DBLP ] DAC, 1995, pp:133-138 [Conf ] Dong Xiang , Srikanth Venkataraman , W. Kent Fuchs , Janak H. Patel Partial Scan Design Based on Circuit State Information. [Citation Graph (0, 0)][DBLP ] DAC, 1996, pp:807-812 [Conf ] Amit R. Pandey , Janak H. Patel An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:368-375 [Conf ] Elizabeth M. Rudnick , John G. Holm , Daniel G. Saab , Janak H. Patel Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP ] EDAC-ETC-EUROASIC, 1994, pp:40-45 [Conf ] Hungse Cha , Elizabeth M. Rudnick , Gwan S. Choi , Janak H. Patel , Ravishankar K. Iyer A Fast and Accurate Gate-Level Transient Fault Simulation Environment. [Citation Graph (0, 0)][DBLP ] FTCS, 1993, pp:310-319 [Conf ] Ilker Hamzaoglu , Janak H. Patel Reducing Test Application Time for Full Scan Embedded Cores. [Citation Graph (0, 0)][DBLP ] FTCS, 1999, pp:260-267 [Conf ] Jaushin Lee , Janak H. Patel An Architectural Level Test Generator for a Hierarchical Design Environment. [Citation Graph (0, 0)][DBLP ] FTCS, 1991, pp:44-51 [Conf ] Irith Pomeranz , Sudhakar M. Reddy , Janak H. Patel Theory and Practice of Sequential Machine Testing and Testability. [Citation Graph (0, 0)][DBLP ] FTCS, 1993, pp:330-337 [Conf ] Gurjeet S. Saund , Michael S. Hsiao , Janak H. Patel Partial Scan beyond Cycle Cutting. [Citation Graph (0, 0)][DBLP ] FTCS, 1997, pp:320-328 [Conf ] Paul J. Thadikaran , Sreejit Chakravarty , Janak H. Patel Fault Simulation ofIDDQ Tests for Bridging Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] FTCS, 1995, pp:340-349 [Conf ] Irith Pomeranz , Sudhakar M. Reddy , Janak H. Patel On Double Transition Faults as a Delay Fault Model. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1996, pp:282-287 [Conf ] John W. C. Fu , Janak H. Patel Trace Driven Simulation using Sampled Traces. [Citation Graph (0, 0)][DBLP ] HICSS (1), 1994, pp:211-220 [Conf ] Vivek Chickermane , Jaushin Lee , Janak H. Patel A comparative study of design for testability methods using high-level and gate-level descriptions. [Citation Graph (0, 0)][DBLP ] ICCAD, 1992, pp:620-624 [Conf ] Vivek Chickermane , Janak H. Patel A Fault Oriented Partial Scan Design Approach. [Citation Graph (0, 0)][DBLP ] ICCAD, 1991, pp:400-403 [Conf ] Abhijit Dharchoudhury , Sung-Mo Kang , H. Cha , J. H. Patel Fast timing simulation of transient faults in digital circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 1994, pp:719-722 [Conf ] Gary S. Greenstein , Janak H. Patel E-PROOFS: a CMOS bridging fault simulator. [Citation Graph (0, 0)][DBLP ] ICCAD, 1992, pp:268-271 [Conf ] Ilker Hamzaoglu , Janak H. Patel Deterministic Test Pattern Generation Techniques for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 2000, pp:538-543 [Conf ] Ilker Hamzaoglu , Janak H. Patel Test set compaction algorithms for combinational circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 1998, pp:283-289 [Conf ] Keerthi Heragu , Janak H. Patel , Vishwani D. Agrawal SIGMA: a simulator for segment delay faults. [Citation Graph (0, 0)][DBLP ] ICCAD, 1996, pp:502-508 [Conf ] Keerthi Heragu , Janak H. Patel , Vishwani D. Agrawal Fast identification of untestable delay faults using implications. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:642-647 [Conf ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel Effects of delay models on peak power estimation of VLSI sequential circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:45-51 [Conf ] Frank F. Hsu , Janak H. Patel High-level variable selection for partial-scan implementation. [Citation Graph (0, 0)][DBLP ] ICCAD, 1998, pp:79-84 [Conf ] Frank F. Hsu , Elizabeth M. Rudnick , Janak H. Patel Enhancing high-level control-flow for improved testability. [Citation Graph (0, 0)][DBLP ] ICCAD, 1996, pp:322-328 [Conf ] Jaushin Lee , Janak H. Patel A Signal-Driven Discrete Relaxation Technique for Architectural Level Test Generation. [Citation Graph (0, 0)][DBLP ] ICCAD, 1991, pp:458-461 [Conf ] Rabindra K. Roy , Abhijit Chatterjee , Janak H. Patel , Jacob A. Abraham , Manuel A. d'Abreu Automatic test generation for linear digital systems with bi-level search using matrix transform methods. [Citation Graph (0, 0)][DBLP ] ICCAD, 1992, pp:224-228 [Conf ] Elizabeth M. Rudnick , Thomas M. Niermann , Janak H. Patel Methods for Reducing Events in Sequential Circuit Fault Simulation. [Citation Graph (0, 0)][DBLP ] ICCAD, 1991, pp:546-549 [Conf ] Elizabeth M. Rudnick , Janak H. Patel Simulation-based techniques for dynamic test sequence compaction. [Citation Graph (0, 0)][DBLP ] ICCAD, 1996, pp:67-73 [Conf ] Hungse Cha , Janak H. Patel A Logic-Level Model for alpha-Paricle Hits in CMOS Circuits. [Citation Graph (0, 0)][DBLP ] ICCD, 1993, pp:538-542 [Conf ] Hungse Cha , Janak H. Patel Latch Design for Transient Pulse Tolerance. [Citation Graph (0, 0)][DBLP ] ICCD, 1994, pp:385-388 [Conf ] Michael S. Hsiao , Janak H. Patel A new architectural-level fault simulation using propagation prediction of grouped fault-effects. [Citation Graph (0, 0)][DBLP ] ICCD, 1995, pp:628-0 [Conf ] Liyang Lai , Janak H. Patel , Thomas Rinderknecht , Wu-Tung Cheng Hardware Ef.cient LBISTWith Complementary Weights. [Citation Graph (0, 0)][DBLP ] ICCD, 2005, pp:479-484 [Conf ] Steven Parkes , Prithviraj Banerjee , Janak H. Patel A parallel algorithm for fault simulation based on PROOFS . [Citation Graph (0, 0)][DBLP ] ICCD, 1995, pp:616-0 [Conf ] Santosh G. Abraham , Janak H. Patel Parallel Garbage Collection on a Virtual Memory System. [Citation Graph (0, 0)][DBLP ] ICPP, 1987, pp:243-246 [Conf ] Jeff Baxter , Janak H. Patel The LAST Algorithm: A Heuristic-Based Static Task Allocation Algorithm. [Citation Graph (0, 0)][DBLP ] ICPP (2), 1989, pp:217-222 [Conf ] Jeff Baxter , Balkrishna Ramkumar , Janak H. Patel Compile Time Parallel Resource Allocation for Unbounded Tree Structure Task Graphs. [Citation Graph (0, 0)][DBLP ] ICPP (1), 1992, pp:202-209 [Conf ] Alok N. Choudhary , Janak H. Patel A Parallel Processing Architecture for an Integrated Vision System. [Citation Graph (0, 0)][DBLP ] ICPP (1), 1988, pp:383-387 [Conf ] Alok N. Choudhary , Janak H. Patel Performance Evaluation of Clusters of NETRA: An Architecture for Computer Vision Systems. [Citation Graph (0, 0)][DBLP ] ICPP (1), 1990, pp:494-497 [Conf ] John W. C. Fu , Janak H. Patel Memory Reference Behavior of Compiler Optimized Programs on High Speed. [Citation Graph (0, 0)][DBLP ] ICPP, 1993, pp:87-94 [Conf ] Kun-Lung Wu , W. Kent Fuchs , Janak H. Patel Cache-Based Error Recovery for Shared Memory Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] ICPP (1), 1989, pp:159-166 [Conf ] Ravishankar K. Iyer , William H. Sanders , Janak H. Patel , Zbigniew Kalbarczyk The evolution of dependable computing at the University of Illinois. [Citation Graph (0, 0)][DBLP ] IFIP Congress Topical Sessions, 2004, pp:135-164 [Conf ] John W. C. Fu , Janak H. Patel Data Prefetching Strategies for Vector Cache Memories. [Citation Graph (0, 0)][DBLP ] IPPS, 1991, pp:555-560 [Conf ] Jeff Baxter , Janak H. Patel Profiling Based Task Migration. [Citation Graph (0, 0)][DBLP ] IPPS, 1992, pp:192-195 [Conf ] Jeff Baxter , John W. C. Fu , Balkrishna Ramkumar , Janak H. Patel Hybrid Resource Management Algorithms for Multicomputer Systems. [Citation Graph (0, 0)][DBLP ] IPPS, 1994, pp:482-489 [Conf ] Alfred Brenner , Richard F. Freund , R. Stockton Gaines , Rob Kelly , Louis Lome , Richard McAndrew , Alexandru Nicolau , Janak H. Patel , Thomas Probert , John H. Reif , Jorge L. C. Sanz , Howard Jay Siegel , Jon A. Webb How Do We Make Parallel Processing a Reality? Bridging the Gap Between Theory and Practice. [Citation Graph (0, 0)][DBLP ] IPPS, 1991, pp:648-653 [Conf ] Richard J. Eickemeyer , Janak H. Patel Performance Evaluation of Multiple Register Sets. [Citation Graph (0, 0)][DBLP ] ISCA, 1987, pp:264-271 [Conf ] Richard J. Eickemeyer , Janak H. Patel Performance Evaluation of On-Chip Register and Cache Organizations. [Citation Graph (0, 0)][DBLP ] ISCA, 1988, pp:64-72 [Conf ] Mohammad Malkawi , Janak H. Patel Performance Measurement of Paging Behavior in Multiprogramming Systems. [Citation Graph (0, 0)][DBLP ] ISCA, 1986, pp:111-118 [Conf ] Mark S. Papamarcos , Janak H. Patel A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories. [Citation Graph (0, 0)][DBLP ] ISCA, 1984, pp:348-354 [Conf ] Mark S. Papamarcos , Janak H. Patel A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories. [Citation Graph (0, 0)][DBLP ] 25 Years ISCA: Retrospectives and Reprints, 1998, pp:284-290 [Conf ] Janak H. Patel Pipelines wth Internal Buffers. [Citation Graph (0, 0)][DBLP ] ISCA, 1978, pp:249-255 [Conf ] Janak H. Patel Processor-Memory Interconnections for Multiprocessors. [Citation Graph (0, 0)][DBLP ] ISCA, 1979, pp:168-177 [Conf ] Janak H. Patel Retrospective: Improving the Throughput of a Pipeline by Insertion of Delays. [Citation Graph (0, 0)][DBLP ] 25 Years ISCA: Retrospectives and Reprints, 1998, pp:5- [Conf ] Janak H. Patel Retrospective: A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories. [Citation Graph (0, 0)][DBLP ] 25 Years ISCA: Retrospectives and Reprints, 1998, pp:39-41 [Conf ] Janak H. Patel , Edward S. Davidson Improving the Throughput of a Pipeline by Insertion of Delays. [Citation Graph (0, 0)][DBLP ] ISCA, 1976, pp:159-164 [Conf ] Janak H. Patel , Edward S. Davidson Improving the Throughput of a Pipeline by Insertion of Delays. [Citation Graph (0, 0)][DBLP ] 25 Years ISCA: Retrospectives and Reprints, 1998, pp:132-137 [Conf ] Ashwin Ram , Janak H. Patel Parallel Garbage Collection Without Synchronization Overhead. [Citation Graph (0, 0)][DBLP ] ISCA, 1985, pp:84-90 [Conf ] Gurindar S. Sohi , Edward S. Davidson , Janak H. Patel An Efficient LISP-Execution Architecture with a New Representation for List Structures. [Citation Graph (0, 0)][DBLP ] ISCA, 1985, pp:91-98 [Conf ] Phil C. C. Yeh , Janak H. Patel , Edward S. Davidson Performance of Shared Cache for Parallel-Pipelined Computer Systems [Citation Graph (0, 0)][DBLP ] ISCA, 1983, pp:117-123 [Conf ] Pi-Yu Chung , Ibrahim N. Hajj , Janak H. Patel Efficient Variable Ordering Heuristics for Shared ROBDD. [Citation Graph (0, 0)][DBLP ] ISCAS, 1993, pp:1690-1693 [Conf ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel K2: an estimator for peak sustainable power of VLSI circuits. [Citation Graph (0, 0)][DBLP ] ISLPED, 1997, pp:178-183 [Conf ] Frank F. Hsu , Elizabeth M. Rudnick , Janak H. Patel Testability Insertion in Behavioral Descriptions. [Citation Graph (0, 0)][DBLP ] ISSS, 1996, pp:139-144 [Conf ] Mihir A. Shah , Janak H. Patel Enhancement of the Illinois Scan Architecture for Use with Multiple Scan Inputs. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2004, pp:167-172 [Conf ] Wu-Tung Cheng , Janak H. Patel Multiple-Fault Detection in Iterative Logic Arrays. [Citation Graph (0, 0)][DBLP ] ITC, 1985, pp:493-499 [Conf ] Vivek Chickermane , Jaushin Lee , Janak H. Patel Design for Testability Using Architectural Descriptions. [Citation Graph (0, 0)][DBLP ] ITC, 1992, pp:752-761 [Conf ] James P. Cusey , Janak H. Patel BART: A Bridging Fault Test Generation for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1997, pp:838-847 [Conf ] Ramaswami Dandapani , Janak H. Patel , Jacob A. Abraham Design of Test Pattern Generators for Built-In Test. [Citation Graph (0, 0)][DBLP ] ITC, 1984, pp:315-319 [Conf ] Ilker Hamzaoglu , Janak H. Patel Compact two-pattern test set generation for combinational and full scan circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1998, pp:944-953 [Conf ] Frank F. Hsu , Kenneth M. Butler , Janak H. Patel A case study on the implementation of the Illinois Scan Architecture. [Citation Graph (0, 0)][DBLP ] ITC, 2001, pp:538-547 [Conf ] Liyang Lai , Janak H. Patel , Thomas Rinderknecht , Wu-Tung Cheng Logic BIST with Scan Chain Segmentation. [Citation Graph (0, 0)][DBLP ] ITC, 2004, pp:57-66 [Conf ] Jaushin Lee , Janak H. Patel ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:729-738 [Conf ] Jaushin Lee , Janak H. Patel An Instruction Sequence Assembling Methodology for Testing Microprocessors. [Citation Graph (0, 0)][DBLP ] ITC, 1992, pp:49-58 [Conf ] Jeff Rearick , Janak H. Patel Fast and Accurate CMOS Bridging Fault Simulation. [Citation Graph (0, 0)][DBLP ] ITC, 1993, pp:54-62 [Conf ] Elizabeth M. Rudnick , W. Kent Fuchs , Janak H. Patel Diagnostic Fault Simulation of Sequential Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1992, pp:178-186 [Conf ] Elizabeth M. Rudnick , Janak H. Patel Putting the Squeeze on Test Sequences. [Citation Graph (0, 0)][DBLP ] ITC, 1997, pp:723-732 [Conf ] Elizabeth M. Rudnick , Janak H. Patel , Irith Pomeranz On Potential Fault Detection in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1996, pp:142-149 [Conf ] Manish Sharma , Janak H. Patel Enhanced delay defect coverage with path-segments. [Citation Graph (0, 0)][DBLP ] ITC, 2000, pp:385-392 [Conf ] Manish Sharma , Janak H. Patel Testing of critical paths for delay faults. [Citation Graph (0, 0)][DBLP ] ITC, 2001, pp:634-641 [Conf ] Manish Sharma , Janak H. Patel Finding a Small Set of Longest Testable Paths that Cover Every Gate. [Citation Graph (0, 0)][DBLP ] ITC, 2002, pp:974-982 [Conf ] Dong Xiang , Janak H. Patel A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information. [Citation Graph (0, 0)][DBLP ] ITC, 1996, pp:548-557 [Conf ] John W. C. Fu , Janak H. Patel , Bob L. Janssens Stride directed prefetching in scalar processors. [Citation Graph (0, 0)][DBLP ] MICRO, 1992, pp:102-110 [Conf ] Dilip Krishnaswamy , Prithviraj Banerjee , Elizabeth M. Rudnick , Janak H. Patel Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation. [Citation Graph (0, 0)][DBLP ] Workshop on Parallel and Distributed Simulation, 1997, pp:30-37 [Conf ] Mohammad Malkawi , Janak H. Patel Compiler Directed Memory Management Policy For Numerical Programs. [Citation Graph (0, 0)][DBLP ] SOSP, 1985, pp:97-106 [Conf ] Keerthi Heragu , Janak H. Patel , Vishwani D. Agrawal Improving accuracy in path delay fault coverage estimation. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1996, pp:422-425 [Conf ] Keerthi Heragu , Janak H. Patel , Vishwani D. Agrawal A Test Generator for Segment Delay Faults. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1999, pp:484-491 [Conf ] Charles R. Graham , Elizabeth M. Rudnick , Janak H. Patel Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1997, pp:542-544 [Conf ] Michael S. Hsiao , Gurjeet S. Saund , Elizabeth M. Rudnick , Janak H. Patel Partial Scan Selection Based on Dynamic Reachability and Observability Information. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1998, pp:174-180 [Conf ] Zbigniew Kalbarczyk , Janak H. Patel , Myeong S. Lee , Ravishankar K. Iyer An Approach to Evaluating the Effects of Realistic Faults in Digital Circuits. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1999, pp:260-265 [Conf ] Dilip Krishnaswamy , Michael S. Hsiao , Vikram Saxena , Elizabeth M. Rudnick , Janak H. Patel , Prithviraj Banerjee Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1997, pp:475-481 [Conf ] Elizabeth M. Rudnick , Janak H. Patel A genetic approach to test application time reduction for full scan and partial scan circuits. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1995, pp:288-293 [Conf ] Elizabeth M. Rudnick , Janak H. Patel Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1997, pp:495-503 [Conf ] Srikanth Venkataraman , W. Kent Fuchs , Janak H. Patel Diagnostic Simulation of Sequential Circuits Using Fault Sampling. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1998, pp:476-481 [Conf ] Jian-Kun Zhao , Jeffrey A. Newquist , Janak H. Patel A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy Identification. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2001, pp:163-0 [Conf ] Vinay Dabholkar , Sreejit Chakravarty , J. Najm , Janak H. Patel Cyclic stress tests for full scan circuits. [Citation Graph (0, 0)][DBLP ] VTS, 1995, pp:89-94 [Conf ] Ilker Hamzaoglu , Janak H. Patel Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:369-376 [Conf ] Ilker Hamzaoglu , Janak H. Patel New Techniques for Deterministic Test Pattern Generation. [Citation Graph (0, 0)][DBLP ] VTS, 1998, pp:446-452 [Conf ] Ismed Hartanto , Vamsi Boppana , Janak H. Patel , W. Kent Fuchs Diagnostic Test Pattern Generation for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] VTS, 1997, pp:196-202 [Conf ] Keerthi Heragu , Janak H. Patel , Vishwani D. Agrawal Segment delay faults: a new fault model. [Citation Graph (0, 0)][DBLP ] VTS, 1996, pp:32-41 [Conf ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel Automatic test generation using genetically-engineered distinguishing sequences. [Citation Graph (0, 0)][DBLP ] VTS, 1996, pp:216-223 [Conf ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors. [Citation Graph (0, 0)][DBLP ] VTS, 1997, pp:188-195 [Conf ] Frank F. Hsu , Janak H. Patel A distance reduction approach to design for testability. [Citation Graph (0, 0)][DBLP ] VTS, 1995, pp:158-163 [Conf ] Dilip Krishnaswamy , Elizabeth M. Rudnick , Janak H. Patel , Prithviraj Banerjee SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation. [Citation Graph (0, 0)][DBLP ] VTS, 1997, pp:274-281 [Conf ] Liyang Lai , Thomas Rinderknecht , Wu-Tung Cheng , Janak H. Patel Logic BIST Using Constrained Scan Cells. [Citation Graph (0, 0)][DBLP ] VTS, 2004, pp:199-205 [Conf ] Terry Lee , Ibrahim N. Hajj , Elizabeth M. Rudnick , Janak H. Patel Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP ] VTS, 1996, pp:456-462 [Conf ] Amit R. Pandey , Janak H. Patel Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs . [Citation Graph (0, 0)][DBLP ] VTS, 2002, pp:9-15 [Conf ] Janak H. Patel , Steven S. Lumetta , Sudhakar M. Reddy Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns. [Citation Graph (0, 0)][DBLP ] VTS, 2003, pp:107-112 [Conf ] Manish Sharma , Janak H. Patel Bounding Circuit Delay by Testing a Very Small Subset of Paths. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:333-342 [Conf ] Manish Sharma , Janak H. Patel What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit? [Citation Graph (0, 0)][DBLP ] VTS, 2004, pp:31-36 [Conf ] Manish Sharma , Janak H. Patel , Jeff Rearick Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture. [Citation Graph (0, 0)][DBLP ] VTS, 2003, pp:15-21 [Conf ] Jian-Kun Zhao , Elizabeth M. Rudnick , Janak H. Patel Static logic implication with application to redundancy identification. [Citation Graph (0, 0)][DBLP ] VTS, 1997, pp:288-295 [Conf ] Hungse Cha , Elizabeth M. Rudnick , Janak H. Patel , Ravishankar K. Iyer , Gwan S. Choi A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:11, pp:1248-1256 [Journal ] Ming-Feng Chang , W. Kent Fuchs , Janak H. Patel Diagnosis and Repair of Memory with Coupling Faults. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1989, v:38, n:4, pp:493-500 [Journal ] Wu-Tung Cheng , Janak H. Patel A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1987, v:36, n:7, pp:891-895 [Journal ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel Fast Static Compaction Algorithms for Sequential Circuit Test Vectors. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1999, v:48, n:3, pp:311-322 [Journal ] Subhasis Laha , Janak H. Patel , Ravishankar K. Iyer Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1988, v:37, n:11, pp:1325-1336 [Journal ] Pinaki Mazumder , Janak H. Patel Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1989, v:38, n:3, pp:394-407 [Journal ] Janak H. Patel An Alternative to the Distributed Pipeline. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1980, v:29, n:8, pp:736-737 [Journal ] Janak H. Patel Performance of Processor-Memory Interconnections for Multiprocessors. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1981, v:30, n:10, pp:771-780 [Journal ] Janak H. Patel Analysis of Multiprocessors with Private Cache Memories. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1982, v:31, n:4, pp:296-304 [Journal ] Janak H. Patel , Leona Y. Fung Concurrent Error Detection in ALU's by Recomputing with Shifted Operands. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1982, v:31, n:7, pp:589-595 [Journal ] Janak H. Patel , Leona Y. Fung Concurrent Error Detection in Multiply and Divide Arrays. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1983, v:32, n:4, pp:417-422 [Journal ] Elizabeth M. Rudnick , Janak H. Patel Efficient Techniques for Dynamic Test Sequence Compaction. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1999, v:48, n:3, pp:323-330 [Journal ] Dong Xiang , Janak H. Patel Partial Scan Design Based on Circuit State Information and Functional Analysis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2004, v:53, n:3, pp:276-287 [Journal ] Phil C. C. Yeh , Janak H. Patel , Edward S. Davidson Shared Cache for Multiple-Stream Computer Systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1983, v:32, n:1, pp:38-47 [Journal ] Susheel J. Chandra , Janak H. Patel Experimental evaluation of testability measures for test generation (logic circuits). [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:1, pp:93-97 [Journal ] Vivek Chickermane , Jaushin Lee , Janak H. Patel Addressing design for testability at the architectural level. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:7, pp:920-934 [Journal ] Ilker Hamzaoglu , Janak H. Patel Test set compaction algorithms for combinational circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:957-963 [Journal ] Keerthi Heragu , Vishwani D. Agrawal , Michael L. Bushnell , Janak H. Patel Improving a nonenumerative method to estimate path delay fault coverage. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:759-762 [Journal ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:239-254 [Journal ] Jaushin Lee , Janak H. Patel Architectural level test generation for microprocessors. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1288-1300 [Journal ] Jaushin Lee , Janak H. Patel Hierarchical test generation under architectural level functional constraints. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1144-1151 [Journal ] Pinaki Mazumder , Janak H. Patel , W. Kent Fuchs Methodologies for testing embedded content addressable memories. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:11-20 [Journal ] Thomas M. Niermann , Wu-Tung Cheng , Janak H. Patel PROOFS: a fast, memory-efficient sequential circuit fault simulator. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:198-207 [Journal ] Thomas M. Niermann , Rabindra K. Roy , Janak H. Patel , Jacob A. Abraham Test compaction for sequential circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:260-267 [Journal ] Elizabeth M. Rudnick , Vivek Chickermane , Janak H. Patel An observability enhancement approach for improved testability and at-speed test. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:1051-1056 [Journal ] Elizabeth M. Rudnick , Janak H. Patel , Gary S. Greenstein , Thomas M. Niermann A genetic algorithm framework for test generation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:1034-1044 [Journal ] Ismed Hartanto , Srikanth Venkataraman , W. Kent Fuchs , Elizabeth M. Rudnick , Janak H. Patel , Sreejit Chakravarty Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:4, pp:471-489 [Journal ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel Dynamic state traversal for sequential circuit test generation. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:548-565 [Journal ] Paul J. Thadikaran , Sreejit Chakravarty , Janak H. Patel Algorithms to compute bridging fault coverage of IDDQ test sets. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:3, pp:281-305 [Journal ] Alok N. Choudhary , Janak H. Patel , Narendra Ahuja NETRA: A Hierarchical and Partitionable Architecture for Computer Vision Systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Parallel Distrib. Syst., 1993, v:4, n:10, pp:1092-1104 [Journal ] Kun-Lung Wu , W. Kent Fuchs , Janak H. Patel Error Recovery in Shared Memory Multiprocessors Using Private Caches. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Parallel Distrib. Syst., 1990, v:1, n:2, pp:231-240 [Journal ] Elizabeth M. Rudnick , Vivek Chickermane , Prithviraj Banerjee , Janak H. Patel Sequential circuit testability enhancement using a nonscan approach. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:333-338 [Journal ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel Peak power estimation of VLSI circuits: new peak power measures. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:435-439 [Journal ] Sequential circuit test generation using dynamic state traversal. [Citation Graph (, )][DBLP ] PROOFS: a super fast fault simulator for sequential circuits. [Citation Graph (, )][DBLP ] A performance model for instruction prefetch in pipelined instruction units. [Citation Graph (, )][DBLP ] Search in 0.009secs, Finished in 0.619secs