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Masaki Hashizume: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada
    CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:117-122 [Conf]
  2. Masaki Hashizume, Toshimasa Kuchii, Takeomi Tamesada
    Supply Current Test for Unit-to-unit Variations of Electrical Characteristics in Gates. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:372-377 [Conf]
  3. Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita
    A High-Speed IDDQ Sensor for Low-Voltage ICs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:327-0 [Conf]
  4. Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita
    A BIST Circuit for IDDQ Tests. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:390-395 [Conf]
  5. Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda
    High speed IDDQ test and its testability for process variation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:344-349 [Conf]
  6. Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
    Identification of Feedback Bridging Faults with Oscillation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:25-0 [Conf]
  7. Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita, Takeomi Tamesada
    I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:112-117 [Conf]
  8. Toshimasa Kuchii, Masaki Hashizume, Takeomi Tamesada
    Algorithmic Test Generation for Supply Current Testing of TTL Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:171-176 [Conf]
  9. Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita
    IDDQ Sensing Technique for High Speed IDDQ Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:111-116 [Conf]
  10. Hiroyuki Yotsuyanagi, Shinsuke Hata, Masaki Hashizume, Takeomi Tamesada
    Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:23-0 [Conf]
  11. Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada
    Test Time Reduction for I DDQ Testing by Arranging Test Vectors. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:423-428 [Conf]
  12. Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
    Reducing Scan Shifts Using Folding Scan Trees. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:6-11 [Conf]
  13. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada
    CMOS open defect detection by supply current test. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:509- [Conf]
  14. Masaki Hashizume, Tetsuo Akita, Hiroyuki Yotsuyanagi, Takeomi Tamesada
    CMOS Open Fault Detection by Appearance Time of Switching Supply Current. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:183-188 [Conf]
  15. Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura
    Current Testable Design of Resistor String DACs. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:197-200 [Conf]
  16. Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi, Takeomi Tamesada
    Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:459-461 [Conf]
  17. Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
    A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:306-311 [Conf]
  18. Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
    Practical Fault Coverage of Supply Current Tests for Bipolar ICs. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:189-194 [Conf]
  19. Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada
    Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:387-391 [Conf]
  20. Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
    On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:269-274 [Conf]
  21. Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Masashi Takeda
    Testability Analysis of IDDQ Testing with Large Threshold Value. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:367-375 [Conf]
  22. Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada
    Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:287-0 [Conf]
  23. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada
    Electric field for detecting open leads in CMOS logic circuits by supply current testing. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2995-2998 [Conf]
  24. Masaki Hashizume, Takeomi Tamesada, Akio Sakamoto
    A Maximum Clique Derivation Algorithm for Simplification of Incompletely Specified Machines. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:193-196 [Conf]
  25. Masaki Hashizume, Takeomi Tamesada, Kazuhiro Yamada, Masaaki Kawakami
    Fault Detection of Combinational Circuits Based on Supply Current. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:374-380 [Conf]
  26. Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
    A test circuit for pin shorts generating oscillation in CMOS logic circuits. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2004, v:35, n:13, pp:10-20 [Journal]
  27. Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
    Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:6, pp:613-620 [Journal]

  28. New Class of Tests for Open Faults with Considering Adjacent Lines. [Citation Graph (, )][DBLP]


  29. Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. [Citation Graph (, )][DBLP]


  30. A Novel Approach for Improving the Quality of Open Fault Diagnosis. [Citation Graph (, )][DBLP]


  31. Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. [Citation Graph (, )][DBLP]


  32. Current-based testable design of level shifters in liquid crystal display drivers. [Citation Graph (, )][DBLP]


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