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Title:
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Thomas W. Williams: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. F. Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu
    DFT closure. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:8-9 [Conf]
  2. Rohit Kapur, Thomas W. Williams
    Manufacturing Test of SoCs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:317-319 [Conf]
  3. Thomas W. Williams
    Design for Testability: The Path to Deep Submicron. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:- [Conf]
  4. Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
    Enhancing test efficiency for delay fault testing using multiple-clocked schemes. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:371-374 [Conf]
  5. Thomas W. Williams, Bill Underwood, M. Ray Mercer
    The Interdependence Between Delay-Optimization of Synthesized Networks and Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:87-92 [Conf]
  6. Rohit Kapur, Thomas W. Williams, M. Ray Mercer
    Directed-Binary Search in Logic BIST Diagnostics. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1121- [Conf]
  7. Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch
    Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10110-10115 [Conf]
  8. Maria Gkatziani, Rohit Kapur, Qing Su, Ben Mathew, Roberto Mattiuzzo, Laura Tarantini, Cy Hay, Salvatore Talluto, Thomas W. Williams
    Accurately Determining Bridging Defects from Layout. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:87-90 [Conf]
  9. José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams
    Fault Modeling and Defect Level Projections in Digital ICs. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:436-442 [Conf]
  10. Nahmsuk Oh, Rohit Kapur, Thomas W. Williams
    Fast seed computation for reseeding shift register in test pattern compression. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:76-81 [Conf]
  11. Li-C. Wang, M. Ray Mercer, Thomas W. Williams
    A Better ATPG Algorithm and Its Design Principles. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:248-253 [Conf]
  12. Thomas W. Williams
    Design for Testability: Today and in the Future. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:14- [Conf]
  13. Thomas W. Williams
    Future Trends in the Testing. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1989, pp:1019-1020 [Conf]
  14. Thomas W. Williams, Rohit Kapur
    Design for Testability in Nanometer Technologies; Searching for Quality. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:167-172 [Conf]
  15. Thomas W. Williams
    EDA to the Rescue of the Silicon Roadmap. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:115-118 [Conf]
  16. Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
    Design of an Efficient Weighted-Random-Pattern Generation System. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:491-500 [Conf]
  17. Rohit Kapur, Thomas W. Williams
    Tester retargetable patterns. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:721-727 [Conf]
  18. Ajay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir
    A new methodology for improved tester utilization. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:916-923 [Conf]
  19. Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
    Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:407-416 [Conf]
  20. Eugen I. Muehldorf, Thomas W. Williams
    Analysis of the Switching Behavior of Combinatorial Logic Networks. [Citation Graph (0, 0)][DBLP]
    ITC, 1982, pp:379-390 [Conf]
  21. Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer
    Delay Testing Quality in Timing-Optimized Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:897-905 [Conf]
  22. Eun Sei Park, Thomas W. Williams, M. Ray Mercer
    Statistical Delay Fault Coverage and Defect Level for Delay Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:492-499 [Conf]
  23. Kenneth D. Wagner, Thomas W. Williams
    Design for Testability of Mixed Signal Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:823-828 [Conf]
  24. Kenneth D. Wagner, Thomas W. Williams
    Enhancing Board Functional Self-Test by Concurrent Sampling. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:633-640 [Conf]
  25. Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir
    Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1041-1050 [Conf]
  26. Li-C. Wang, M. Ray Mercer, Thomas W. Williams
    On Efficiently and Reliably Achieving Low Defective Part Levels. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:616-625 [Conf]
  27. Li-C. Wang, M. Ray Mercer, Thomas W. Williams
    Using Target Faults To Detect Non-Tartget Defects. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:629-638 [Conf]
  28. Thomas W. Williams, R. H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly
    IDDQ Test: Sensitivity Analysis of Scaling. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:786-792 [Conf]
  29. Peter Wohl, John A. Waicukauski, Thomas W. Williams
    Design of compactors for signature-analyzers in built-in self-test. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:54-63 [Conf]
  30. Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams
    A Reconfigurable Shared Scan-in Architecture. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:9-14 [Conf]
  31. Nodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams
    Changing the Scan Enable during Shift. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:73-78 [Conf]
  32. Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams
    On the decline of testing efficiency as fault coverage approaches 100%. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:74-83 [Conf]
  33. Peter Wohl, John A. Waicukauski, Rohit Kapur, S. Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini
    Minimizing the Impact of Scan Compression. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:67-74 [Conf]
  34. Rohit Kapur, Thomas W. Williams
    Tough Challenges as Design and Test Go Nanometer - Guest Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1999, v:32, n:11, pp:42-45 [Journal]
  35. Samitha Samaranayake, Nodari Sitchinava, Rohit Kapur, Minesh B. Amin, Thomas W. Williams
    Dynamic Scan: Driving Down the Cost of Test. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:10, pp:63-68 [Journal]
  36. Thomas W. Williams
    VLSI Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1984, v:17, n:10, pp:126-136 [Journal]
  37. Rohit Kapur, R. Chandramouli, Thomas W. Williams
    Strategies for Low-Cost Test. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:6, pp:47-54 [Journal]
  38. Rohit Kapur, Cy Hay, Thomas W. Williams
    The Mutating Metric for Benchmarking Test. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:3, pp:18-21 [Journal]
  39. Thomas W. Williams
    TTTC recognizes test visionary's lifetime contribution. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:3, pp:282- [Journal]
  40. Eun Sei Park, M. Ray Mercer, Thomas W. Williams
    The Total Delay Fault Model and Statistical Delay Fault Coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:6, pp:688-698 [Journal]
  41. Thomas W. Williams, Kenneth P. Parker
    Design for Testability - A Survey. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:1, pp:2-15 [Journal]
  42. Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
    A weighted random pattern test generation system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:1020-1025 [Journal]
  43. Don MacMillen, Raul Camposano, Dwight D. Hill, Thomas W. Williams
    An industrial view of electronic design automation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:12, pp:1428-1448 [Journal]
  44. José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams
    Defect level evaluation in an IC design environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1286-1293 [Journal]

  45. EDA to the Rescue of the Silicon Roadmap. [Citation Graph (, )][DBLP]


  46. Historical Perspective on Scan Compression. [Citation Graph (, )][DBLP]


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