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Rohit Kapur: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. F. Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu
    DFT closure. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:8-9 [Conf]
  2. Rohit Kapur, Thomas W. Williams
    Manufacturing Test of SoCs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:317-319 [Conf]
  3. Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer
    Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:417-420 [Conf]
  4. Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
    Enhancing test efficiency for delay fault testing using multiple-clocked schemes. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:371-374 [Conf]
  5. M. Ray Mercer, Rohit Kapur, Don E. Ross
    Functional Approaches to Generating Orderings for Efficient Symbolic Representations. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:624-627 [Conf]
  6. Rohit Kapur, Thomas W. Williams, M. Ray Mercer
    Directed-Binary Search in Logic BIST Diagnostics. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1121- [Conf]
  7. Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch
    Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10110-10115 [Conf]
  8. Maria Gkatziani, Rohit Kapur, Qing Su, Ben Mathew, Roberto Mattiuzzo, Laura Tarantini, Cy Hay, Salvatore Talluto, Thomas W. Williams
    Accurately Determining Bridging Defects from Layout. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:87-90 [Conf]
  9. Nahmsuk Oh, Rohit Kapur, Thomas W. Williams
    Fast seed computation for reseeding shift register in test pattern compression. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:76-81 [Conf]
  10. Thomas W. Williams, Rohit Kapur
    Design for Testability in Nanometer Technologies; Searching for Quality. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:167-172 [Conf]
  11. Francisco DaSilva, Yervant Zorian, Lee Whetsel, Karim Arabi, Rohit Kapur
    Overview of the IEEE P1500 Standard. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:988-997 [Conf]
  12. Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur
    Integrating DFT in the Physical Synthesis Flow. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:788-795 [Conf]
  13. Rohit Kapur
    Security vs. Test Quality: Are they mutually exclusive?. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1414- [Conf]
  14. Rohit Kapur
    High level ATPG is important and is on its way! [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1115-1116 [Conf]
  15. Rohit Kapur, Maurice Lousberg, Tony Taylor, Brion L. Keller, Paul Reuter, Douglas Kay
    CTL the language for describing core-based test. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:131-139 [Conf]
  16. Rohit Kapur, Jaehong Park, M. Ray Mercer
    All Tests for a Fault Are Not Equally Valuable for Defect Detection. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:762-769 [Conf]
  17. Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
    Design of an Efficient Weighted-Random-Pattern Generation System. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:491-500 [Conf]
  18. Rohit Kapur, Thomas W. Williams
    Tester retargetable patterns. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:721-727 [Conf]
  19. Ajay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir
    A new methodology for improved tester utilization. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:916-923 [Conf]
  20. Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
    Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:407-416 [Conf]
  21. Thomas W. Williams, R. H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly
    IDDQ Test: Sensitivity Analysis of Scaling. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:786-792 [Conf]
  22. Yervant Zorian, Erik Jan Marinissen, Rohit Kapur
    On using IEEE P1500 SECT for test plug-n-play. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:770-777 [Conf]
  23. Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel
    Towards a standard for embedded core test: an example. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:616-627 [Conf]
  24. Dwayne Burek, Garen Darbinyan, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti
    IP and Automation to Support IEEE P1500. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:411-412 [Conf]
  25. Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams
    A Reconfigurable Shared Scan-in Architecture. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:9-14 [Conf]
  26. Nodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams
    Changing the Scan Enable during Shift. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:73-78 [Conf]
  27. Anshuman Chandra, Haihua Yan, Rohit Kapur
    Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:84-92 [Conf]
  28. Peter Wohl, John A. Waicukauski, Rohit Kapur, S. Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini
    Minimizing the Impact of Scan Compression. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:67-74 [Conf]
  29. Rohit Kapur, Edward F. Miller
    System Test and Reliability: Techniques for Avoiding Failure (Guest Editors' Introduction). [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1996, v:29, n:11, pp:28-30 [Journal]
  30. Rohit Kapur, Thomas W. Williams
    Tough Challenges as Design and Test Go Nanometer - Guest Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1999, v:32, n:11, pp:42-45 [Journal]
  31. Samitha Samaranayake, Nodari Sitchinava, Rohit Kapur, Minesh B. Amin, Thomas W. Williams
    Dynamic Scan: Driving Down the Cost of Test. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:10, pp:63-68 [Journal]
  32. Magdy S. Abadir, Rohit Kapur
    Cost-Driven Ranking of Memory Elements for Partial Intrusion. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:3, pp:45-50 [Journal]
  33. Bruce D. Cory, Rohit Kapur, Bill Underwood
    Speed Binning with Path Delay Test in 150-nm Technology. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:41-45 [Journal]
  34. Rohit Kapur, R. Chandramouli, Thomas W. Williams
    Strategies for Low-Cost Test. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:6, pp:47-54 [Journal]
  35. Rohit Kapur, Cy Hay, Thomas W. Williams
    The Mutating Metric for Benchmarking Test. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:3, pp:18-21 [Journal]
  36. Rohit Kapur, M. Ray Mercer
    Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:12, pp:1580-1588 [Journal]
  37. Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
    A weighted random pattern test generation system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:1020-1025 [Journal]
  38. Rajesh Galivanche, Rohit Kapur, Antonio Rubio
    Testing in the year 2020. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:960-965 [Conf]

  39. Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction. [Citation Graph (, )][DBLP]


  40. Scalable Adaptive Scan (SAS). [Citation Graph (, )][DBLP]


  41. Interval Based X-Masking for Scan Compression Architectures. [Citation Graph (, )][DBLP]


  42. Proactive management of X's in scan chains for compression. [Citation Graph (, )][DBLP]


  43. Bounded Adjacent Fill for Low Capture Power Scan Testing. [Citation Graph (, )][DBLP]


  44. Historical Perspective on Scan Compression. [Citation Graph (, )][DBLP]


  45. CTL and Its Usage in the EDA Industry. [Citation Graph (, )][DBLP]


  46. Conference Reports. [Citation Graph (, )][DBLP]


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