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Title:
Author:
John P. Hayes: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. John P. Hayes
    Faults and Tests in Quantum Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:- [Conf]
  2. John P. Hayes, Ilia Polian, Bernd Becker
    Testing for Missing-Gate Faults in Reversible Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:100-105 [Conf]
  3. Ilia Polian, Thomas Fiehn, Bernd Becker, John P. Hayes
    A Family of Logical Fault Models for Reversible Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:422-427 [Conf]
  4. Nagarajan Kandasamy, Sherif Abdelwahed, Gregory C. Sharp, John P. Hayes
    An Online Control Framework for Designing Self-Optimizing Computing Systems: Application to Power Management. [Citation Graph (0, 0)][DBLP]
    Self-star Properties in Complex Information Systems, 2005, pp:174-188 [Conf]
  5. Michael J. Batek, John P. Hayes
    Test-Set Preserving Logic Transformations. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:454-458 [Conf]
  6. David Van Campenhout, Trevor N. Mudge, John P. Hayes
    High-Level Test Generation for Design Verification of Pipelined Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:185-188 [Conf]
  7. Krishnendu Chakrabarty, John P. Hayes
    DFBT: A Design-for-Testability Method Based on Balance Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:351-357 [Conf]
  8. Feng Gao, John P. Hayes
    Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:31-36 [Conf]
  9. Avaneendra Gupta, John P. Hayes
    CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:452-455 [Conf]
  10. John P. Hayes
    Tutorial: basic concepts in quantum circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:893- [Conf]
  11. R. L. Maiasz, John P. Hayes
    Layout Optimization of CMOS Functional Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:544-551 [Conf]
  12. Robert L. Maziasz, John P. Hayes
    Exact Width and Height Minimization of CMOS Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:487-493 [Conf]
  13. Hakan Yalcin, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Karem A. Sakallah, John P. Hayes
    An Advanced Timing Characterization Method Using Mode Dependency. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:657-660 [Conf]
  14. Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes
    Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:282-287 [Conf]
  15. George F. Viamontes, Igor L. Markov, John P. Hayes
    High-Performance QuIDD-Based Simulation of Quantum Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1354-1355 [Conf]
  16. Nagarajan Kandasamy, John P. Hayes, Brian T. Murray
    Time-Constrained Failure Diagnosis in Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DSN, 2002, pp:449-458 [Conf]
  17. Rajesh Venkatasubramanian, John P. Hayes
    Discovering 1-FT Routes in Mobile Ad Hoc Networks. [Citation Graph (0, 0)][DBLP]
    DSN, 2004, pp:627-636 [Conf]
  18. John P. Hayes
    Minimization of Fanout in Switching Networks [Citation Graph (0, 0)][DBLP]
    FOCS, 1974, pp:133-139 [Conf]
  19. Amit Chowdhary, John P. Hayes
    General Modeling and Technology-Mapping Technique for LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:43-49 [Conf]
  20. Hung-Kuei Ku, John P. Hayes
    Connectivity and Fault Tolerance of Multiple-Bus Systems. [Citation Graph (0, 0)][DBLP]
    FTCS, 1994, pp:372-381 [Conf]
  21. Krishnendu Chakrabarty, John P. Hayes
    Balance Testing of Logic Circuits. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:350-359 [Conf]
  22. Ronald D. Blanton, John P. Hayes
    Efficient Testing of Tree Circuits. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:176-185 [Conf]
  23. Shantanu Dutt, John P. Hayes
    Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:292-299 [Conf]
  24. Nagarajan Kandasamy, Sherif Abdelwahed, John P. Hayes
    Self-Optimization in Computer Systems via On-Line Control: Application to Power Management. [Citation Graph (0, 0)][DBLP]
    ICAC, 2004, pp:54-61 [Conf]
  25. Hussain Al-Asaad, John P. Hayes
    Design verification via simulation and automatic test pattern generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:174-180 [Conf]
  26. Amit Chowdhary, John P. Hayes
    Technology mapping for field-programmable gate arrays using integer programming. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:346-352 [Conf]
  27. Feng Gao, John P. Hayes
    Exact and heuristic approaches to input vector control for leakage power reduction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:527-532 [Conf]
  28. Avaneendra Gupta, John P. Hayes
    Width minimization of two-dimensional CMOS cells using integer programming. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:660-667 [Conf]
  29. Avaneendra Gupta, John P. Hayes
    Optimal 2-D cell layout with integrated transistor folding. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:128-135 [Conf]
  30. Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes
    Reversible logic circuit synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:353-360 [Conf]
  31. Hakan Yalcin, John P. Hayes
    Hierarchical timing analysis using conditional delays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:371-377 [Conf]
  32. Hakan Yalcin, John P. Hayes, Karem A. Sakallah
    An approximate timing analysis method for datapath circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:114-118 [Conf]
  33. Ronald D. Blanton, John P. Hayes
    Properties of the Input Pattern Fault Model. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:372-380 [Conf]
  34. Feng Gao, John P. Hayes
    Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:258-264 [Conf]
  35. Raif M. Yanney, John P. Hayes
    Distributed Recovery in Fault-Tolerant Multiprocessor Networks. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1984, pp:514-525 [Conf]
  36. John P. Hayes, Trevor N. Mudge, Quentin F. Stout
    Architecture of a Hypercube Supercomputer. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:653-660 [Conf]
  37. Ram Raghavan, John P. Hayes
    Scalar-Vector Memory Interference in Vector Computers. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:180-187 [Conf]
  38. Feng Gao, John P. Hayes
    On-Line Monitor Design of Finite-State Machines. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:74-78 [Conf]
  39. Rajesh Venkatasubramanian, John P. Hayes, Brian T. Murray
    Low-Cost On-Line Fault Detection Using Control Flow Assertions. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:137-143 [Conf]
  40. John P. Hayes
    Fault-Tolerant Quantum Computers. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  41. John Paul Shen, John P. Hayes
    Fault Tolerance of a Class of Connecting Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 1980, pp:61-71 [Conf]
  42. Feng Gao, John P. Hayes
    ILP-based optimization of sequential circuits for low power. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:140-145 [Conf]
  43. Krishnendu Chakrabarty, John P. Hayes
    Efficient Test-Response Compression for Multiple-Output Cicuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:501-510 [Conf]
  44. Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes
    Optimal Space Compaction of Test Responses. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:834-843 [Conf]
  45. Mark C. Hansen, John P. Hayes
    High-Level Test Generation Using Symbolic Scheduling. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:586-595 [Conf]
  46. Hyungwon Kim, John P. Hayes
    High-coverage ATPG for datapath circuits with unimplemented blocks. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:577-586 [Conf]
  47. Hyungwon Kim, John P. Hayes
    Delay fault testing of IP-based designs via symbolic path modeling. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1045-1054 [Conf]
  48. Brian T. Murray, John P. Hayes
    Hierarchical Test Generation Using Precomputed Tests for Modules. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:221-229 [Conf]
  49. Brian T. Murray, John P. Hayes
    Test Propagation Through Modules and Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:748-757 [Conf]
  50. Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes
    Reversible Logic Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:125-130 [Conf]
  51. Nagarajan Kandasamy, John P. Hayes, Brian T. Murray
    Dependable Communication Synthesis for Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    SAFECOMP, 2003, pp:275-288 [Conf]
  52. Ram Raghavan, John P. Hayes
    On randomly interleaved memories. [Citation Graph (0, 0)][DBLP]
    SC, 1990, pp:49-58 [Conf]
  53. Nagarajan Kandasamy, John P. Hayes, Brian T. Murray
    Tolerating Transient Faults in Statically Scheduled Safety-Critical Embedded Systems. [Citation Graph (0, 0)][DBLP]
    Symposium on Reliable Distributed Systems, 1999, pp:212-221 [Conf]
  54. Avaneendra Gupta, John P. Hayes
    A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:15-20 [Conf]
  55. Avaneendra Gupta, John P. Hayes
    Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:453-459 [Conf]
  56. R. D. (Shawn) Blanton, John P. Hayes
    Design of a fast, easily testable ALU. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:9-16 [Conf]
  57. Hussain Al-Asaad, John P. Hayes
    ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:221-230 [Conf]
  58. Mark C. Hansen, John P. Hayes
    High-level test generation using physically-induced faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:20-28 [Conf]
  59. Hyungwon Kim, John P. Hayes
    Delay Fault Testing of Designs with Embedded IP Cores. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:160-167 [Conf]
  60. Ketan N. Patel, John P. Hayes, Igor L. Markov
    Fault Testing for Reversible Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:410-416 [Conf]
  61. John P. Hayes, Ilia Polian, Bernd Becker
    An Analysis Framework for Transient-Error Tolerance. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:249-255 [Conf]
  62. Raif M. Yanney, John P. Hayes
    Fault Recovery in Distributed Processing Loop Networks. [Citation Graph (0, 0)][DBLP]
    Computer Networks, 1988, v:15, n:, pp:229-243 [Journal]
  63. Debashis Bhattacharya, Brian T. Murray, John P. Hayes
    High-Level Test Generation for VLSI. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1989, v:22, n:4, pp:16-24 [Journal]
  64. Brian T. Murray, John P. Hayes
    Testing ICs: Getting to the Core of the Problem. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1996, v:29, n:11, pp:32-38 [Journal]
  65. Hussain Al-Asaad, Brian T. Murray, John P. Hayes
    Online BIST for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:4, pp:17-24 [Journal]
  66. David Van Campenhout, Trevor N. Mudge, John P. Hayes
    Collection and Analysis of Microprocessor Design Errors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:51-60 [Journal]
  67. Mark C. Hansen, Hakan Yalcin, John P. Hayes
    Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:3, pp:72-80 [Journal]
  68. Pinaki Mazumder, John P. Hayes
    Guest Editor's Introduction: Testing and Improving the Testability of Multimegabit Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:1, pp:6-7 [Journal]
  69. John P. Hayes
    The Fanout Structure of Switching Functions. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1975, v:22, n:4, pp:551-571 [Journal]
  70. John P. Hayes
    Enumeration of Fanout-Free Boolean Functions. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1976, v:23, n:4, pp:700-709 [Journal]
  71. Aditya K. Prasad, Vivek V. Shende, Igor L. Markov, John P. Hayes, Ketan N. Patel
    Data structures and algorithms for simplifying reversible circuits. [Citation Graph (0, 0)][DBLP]
    JETC, 2006, v:2, n:4, pp:277-293 [Journal]
  72. Shantanu Dutt, John P. Hayes
    Designing Fault-Tolerant System Using Automorphisms. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1991, v:12, n:3, pp:249-268 [Journal]
  73. Tze Chiang Lee, John P. Hayes
    Design of Gracefully Degradable Hypercube-Connected Systems. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1992, v:14, n:4, pp:390-401 [Journal]
  74. Trevor N. Mudge, John P. Hayes, Gregory D. Buzzard, Donald C. Winsor
    Analysis of Multiple-Bus Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1986, v:3, n:3, pp:328-343 [Journal]
  75. Hung-Kuei Ku, John P. Hayes
    Optimally edge fault-tolerant trees. [Citation Graph (0, 0)][DBLP]
    Networks, 1996, v:27, n:3, pp:203-214 [Journal]
  76. Frank Harary, John P. Hayes
    Node fault tolerance in graphs. [Citation Graph (0, 0)][DBLP]
    Networks, 1996, v:27, n:1, pp:19-23 [Journal]
  77. John Paul Shen, John P. Hayes, Luigi Ciminiera, Angelo Serra
    Fault-tolerance and performance analysis of beta-networks. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1986, v:3, n:3, pp:231-249 [Journal]
  78. Ronald D. Blanton, John P. Hayes
    Testability of Convergent Tree Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:8, pp:950-963 [Journal]
  79. Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes
    Optimal Zero-Aliasing Space Compaction of Test Responses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:11, pp:1171-1187 [Journal]
  80. Shantanu Dutt, John P. Hayes
    On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:4, pp:490-503 [Journal]
  81. Shantanu Dutt, John P. Hayes
    Subcube Allocation in Hypercube Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:3, pp:341-352 [Journal]
  82. Shantanu Dutt, John P. Hayes
    Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:5, pp:588-598 [Journal]
  83. Ayee Goundan, John P. Hayes
    Design of Totally Fault Locatable Combinational Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:1, pp:33-44 [Journal]
  84. Ayee Goundan, John P. Hayes
    Identification of Equivalent Faults in Logic Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:11, pp:978-985 [Journal]
  85. John P. Hayes
    Detection of Pattern-Sensitive Faults in Random-Access Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1975, v:24, n:2, pp:150-157 [Journal]
  86. John P. Hayes
    Transition Count Testing of Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:6, pp:613-620 [Journal]
  87. John P. Hayes
    A Graph Model for Fault-Tolerant Computing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:9, pp:875-884 [Journal]
  88. John P. Hayes
    On the Properties of Irredundant Logic Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:9, pp:884-892 [Journal]
  89. John P. Hayes
    Generation of Optimal Transition Count Tests. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:1, pp:36-41 [Journal]
  90. John P. Hayes
    Path Complexity of Logic Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:5, pp:459-462 [Journal]
  91. John P. Hayes
    Testing Memories for Single-Cell Pattern-Sensitive Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:3, pp:249-254 [Journal]
  92. John P. Hayes
    Uncertainty, Energy, and Multiple-Valued Logics. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:2, pp:107-114 [Journal]
  93. John P. Hayes
    Pseudo-Boolean Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:7, pp:602-612 [Journal]
  94. Hung-Kuei Ku, John P. Hayes
    Systematic Design of Fault-Tolerant Multiprocessors with Shared Buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:4, pp:439-455 [Journal]
  95. Musaravakkam S. Krishnan, John P. Hayes
    An Array Layout Methodology for VLlSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:12, pp:1055-1067 [Journal]
  96. Tze Chiang Lee, John P. Hayes
    A Fault-Tolerant Communication Scheme for Hypercube Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:10, pp:1242-1256 [Journal]
  97. Ram Raghavan, John P. Hayes
    Reducing Inerference Among Vector Accesses in Interleaved Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:4, pp:471-483 [Journal]
  98. John Paul Shen, John P. Hayes
    Fault-Tolerance of Dynamic-Full-Access Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:3, pp:241-248 [Journal]
  99. Thirumalai Sridhar, John P. Hayes
    A Functional Approach to Testing Bit-Sliced Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:8, pp:563-571 [Journal]
  100. Thirumalai Sridhar, John P. Hayes
    Design of Easily Testable Bit-Sliced Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:11, pp:842-854 [Journal]
  101. Raif M. Yanney, John P. Hayes
    Distributed Recovery in Fault-Tolerant Multiprocessor Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:10, pp:871-879 [Journal]
  102. Debashis Bhattacharya, John P. Hayes
    Designing for high-level test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:752-766 [Journal]
  103. Eduard Cerny, John P. Hayes, Nicholas C. Rumin
    Accuracy of magnitude-class calculations in switch-level modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:443-452 [Journal]
  104. Krishnendu Chakrabarty, John P. Hayes
    Test response compaction using multiplexed parity trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:11, pp:1399-1408 [Journal]
  105. Krishnendu Chakrabarty, John P. Hayes
    On the quality of accumulator-based compaction of test responses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:916-922 [Journal]
  106. Amit Chowdhary, John P. Hayes
    Area-optimal technology mapping for field-programmable gate arrays based on lookup tables. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:999-1013 [Journal]
  107. Feng Gao, John P. Hayes
    Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2564-2571 [Journal]
  108. John P. Hayes
    Fault Modeling for Digital MOS Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:200-208 [Journal]
  109. John P. Hayes
    Digital Simulation with Multiple Logic Values. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:2, pp:274-283 [Journal]
  110. Hyungwon Kim, John P. Hayes
    Realization-independent ATPG for designs with unimplemented blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:290-306 [Journal]
  111. Musaravakkam S. Krishnan, John P. Hayes
    A normalized-area measure for VLSI layouts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:3, pp:411-419 [Journal]
  112. Robert L. Maziasz, John P. Hayes
    Layout optimization of static CMOS functional cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:708-719 [Journal]
  113. Brian T. Murray, John P. Hayes
    Hierarchical test generation using precomputed tests for modules. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:6, pp:594-603 [Journal]
  114. Ketan N. Patel, John P. Hayes, Igor L. Markov
    Fault testing for reversible circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1220-1230 [Journal]
  115. Joonhwan Yi, John P. Hayes
    High-level delay test generation for modular circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:576-590 [Journal]
  116. Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes
    Synthesis of reversible logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:710-722 [Journal]
  117. Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah, John P. Hayes
    Fast and accurate timing characterization using functionalinformation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:315-331 [Journal]
  118. Y. You, John P. Hayes
    Implementation of VLSI self-testing by regularization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:12, pp:1261-1271 [Journal]
  119. Ronald D. Blanton, John P. Hayes
    On the properties of the input pattern fault model. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:1, pp:108-124 [Journal]
  120. Avaneendra Gupta, John P. Hayes
    CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:510-547 [Journal]
  121. David Van Campenhout, Hussain Al-Asaad, John P. Hayes, Trevor N. Mudge, Richard B. Brown
    High-level design verification of microprocessors via error modeling. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:4, pp:581-599 [Journal]
  122. Amit Chowdhary, John P. Hayes
    General technology mapping for field-programmable gate arrays based on lookup tables. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:1-32 [Journal]
  123. Hakan Yalcin, John P. Hayes
    Event propagation conditions in circuit delay computation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:3, pp:249-280 [Journal]
  124. Hung-Kuei Ku, John P. Hayes
    Connective Fault Tolerance in Multiple-Bus Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:6, pp:574-586 [Journal]
  125. Nagarajan Kandasamy, John P. Hayes, Brian T. Murray
    Time-Constrained Failure Diagnosis in Distributed Embedded Systems: Application to Actuator Diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:3, pp:258-270 [Journal]
  126. Ramashis Das, Igor L. Markov, John P. Hayes
    On-Chip Test Generation Using Linear Subspaces. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:111-116 [Conf]
  127. Krishnendu Chakrabarty, John P. Hayes
    Cumulative balance testing of logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:72-83 [Journal]
  128. Krishnendu Chakrabarty, John P. Hayes
    Zero-aliasing space compaction of test responses using multiple parity signatures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:309-313 [Journal]
  129. Ronald D. Blanton, John P. Hayes
    On the design of fast, easily testable ALU's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:220-223 [Journal]
  130. Hyungwon Kim, John P. Hayes
    Delay fault testing of IP-based designs via symbolic path modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:661-678 [Journal]
  131. Feng Gao, John P. Hayes
    Gate Sizing and Vt Assignment for Active-Mode Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:230-239 [Journal]
  132. Joonhwan Yi, John P. Hayes
    The Coupling Model for Function and Delay Faults. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:6, pp:631-649 [Journal]

  133. On the role of timing masking in reliable logic circuit design. [Citation Graph (, )][DBLP]


  134. Improving testability and soft-error resilience through retiming. [Citation Graph (, )][DBLP]


  135. The input pattern fault model and its application. [Citation Graph (, )][DBLP]


  136. Contactless testing: Possibility or pipe-dream? [Citation Graph (, )][DBLP]


  137. On-line sensing for healthier FPGA systems. [Citation Graph (, )][DBLP]


  138. Checking equivalence of quantum circuits and states. [Citation Graph (, )][DBLP]


  139. Enhancing design robustness with reliability-aware resynthesis and logic simulation. [Citation Graph (, )][DBLP]


  140. On-line characterization and reconfiguration for single event upset variations. [Citation Graph (, )][DBLP]


  141. Power-Aware Link Maintenance (PALM) for Mobile Ad Hoc Networks. [Citation Graph (, )][DBLP]


  142. Optimizing router locations for minimum-energy wireless networks. [Citation Graph (, )][DBLP]


  143. Tracking Uncertainty with Probabilistic Logic Circuit Testing. [Citation Graph (, )][DBLP]


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