The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Ilia Polian: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. John P. Hayes, Ilia Polian, Bernd Becker
    Testing for Missing-Gate Faults in Reversible Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:100-105 [Conf]
  2. Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker
    On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:266-271 [Conf]
  3. Ilia Polian, Wolfgang Günther, Bernd Becker
    Efficient Pattern-Based Verification of Connections to IP Cores . [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:443-448 [Conf]
  4. Ilia Polian, Thomas Fiehn, Bernd Becker, John P. Hayes
    A Family of Logical Fault Models for Reversible Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:422-427 [Conf]
  5. Ilia Polian, Irith Pomeranz, Bernd Becker
    Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:2-14 [Conf]
  6. Ilia Polian, Bernd Becker, Sudhakar M. Reddy
    Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11184-11185 [Conf]
  7. Ilia Polian, Alejandro Czutro, Bernd Becker
    Evolutionary Optimization in Code-Based Test Compression. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1124-1129 [Conf]
  8. Ilia Polian, Hideo Fujiwara
    Functional constraints vs. test compression in scan-based delay testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1039-1044 [Conf]
  9. Jochen Eisinger, Ilia Polian, Bernd Becker, Alexander Metzner, Stephan Thesing, Reinhard Wilhelm
    Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:15-20 [Conf]
  10. Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara
    Low-Cost Hardening of Image Processing Applications Against Soft Errors. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:274-279 [Conf]
  11. Ilia Polian, Bernd Becker
    Stop & Go BIST. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:147-151 [Conf]
  12. Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker
    Sequential n -Detection Criteria: Keep It Simple. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:189- [Conf]
  13. Sandip Kundu, Ilia Polian
    An Improved Technique for Reducing False Alarms Due to Soft Errors. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:105-110 [Conf]
  14. Ilia Polian, Piet Engelke, Bernd Becker
    Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:216-0 [Conf]
  15. Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
    Simulating Resistive Bridging and Stuck-At Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1051-1059 [Conf]
  16. Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
    X-Masking During Logic BIST and Its Impact on Defect Coverage. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:442-451 [Conf]
  17. Ilia Polian, Bernd Becker
    Reducing ATE Cost in System-on-Chip Test. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:337-342 [Conf]
  18. Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
    The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:171-178 [Conf]
  19. Ilia Polian, Bernd Becker
    Multiple Scan Chain Design for Two-Pattern Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:88-93 [Conf]
  20. Ilia Polian, Sandip Kundu, Jean Marc Galliere, Piet Engelke, Michel Renovell, Bernd Becker
    Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:343-348 [Conf]
  21. John P. Hayes, Ilia Polian, Bernd Becker
    An Analysis Framework for Transient-Error Tolerance. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:249-255 [Conf]
  22. Ilia Polian, Wolfgang Günther, Bernd Becker
    Pattern-based verification of connections to intellectual property cores. [Citation Graph (0, 0)][DBLP]
    Integration, 2003, v:35, n:1, pp:25-44 [Journal]
  23. Ilia Polian
    Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerechter Entwurf, industrielle Anwendungen (On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2005, v:47, n:3, pp:172-174 [Journal]
  24. Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
    Simulating Resistive-Bridging and Stuck-At Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2181-2192 [Journal]
  25. Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke
    X-masking during logic BIST and its impact on defect coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:2, pp:193-202 [Journal]
  26. Ilia Polian, Damian Nowroth, Bernd Becker
    Identification of Critical Errors in Imaging Applications. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:201-202 [Conf]
  27. Ilia Polian, Alejandro Czutro, Bernd Becker
    Evolutionary Optimization in Code-Based Test Compression [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  28. Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich
    DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2006, v:48, n:5, pp:304-0 [Journal]
  29. Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
    Modeling Feedback Bridging Faults with Non-Zero Resistance. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:1, pp:57-69 [Journal]
  30. Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
    Automatic Test Pattern Generation for Resistive Bridging Faults. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:1, pp:61-69 [Journal]

  31. Dynamic Compaction in SAT-Based ATPG. [Citation Graph (, )][DBLP]


  32. Resistive Bridging Fault Simulation of Industrial Circuits. [Citation Graph (, )][DBLP]


  33. Analysis and optimization of fault-tolerant embedded systems with hardened processors. [Citation Graph (, )][DBLP]


  34. Diagnosis of Realistic Defects Based on the X-Fault Model. [Citation Graph (, )][DBLP]


  35. Selective Hardening of NanoPLA Circuits. [Citation Graph (, )][DBLP]


  36. On Reducing Circuit Malfunctions Caused by Soft Errors. [Citation Graph (, )][DBLP]


  37. A study of cognitive resilience in a JPEG compressor. [Citation Graph (, )][DBLP]


  38. Reducing temperature variability by routing heat pipes. [Citation Graph (, )][DBLP]


  39. Power Droop Testing. [Citation Graph (, )][DBLP]


  40. ATPG-based grading of strong fault-secureness. [Citation Graph (, )][DBLP]


  41. Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. [Citation Graph (, )][DBLP]


  42. TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. [Citation Graph (, )][DBLP]


  43. Automatic Test Pattern Generation for Interconnect Open Defects. [Citation Graph (, )][DBLP]


  44. A Definition and Classification of Timing Anomalies. [Citation Graph (, )][DBLP]


  45. Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors [Citation Graph (, )][DBLP]


  46. Power Droop Testing. [Citation Graph (, )][DBLP]


Search in 0.017secs, Finished in 0.018secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002