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Publications of Author

1. Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
   Hybrid BIST Test Scheduling Based on Defect Probabilities. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2004, pp:230-235 [Conf]
   
2. Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
   Test Time Minimization for Hybrid BIST of Core-Based Systems. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2003, pp:318-325 [Conf]
   
3. Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
   Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. [Citation Graph (0, 0)][DBLP]
   DFT, 2003, pp:225-0 [Conf]
   
4. Gert Jervan, Zebo Peng, Raimund Ubar
   Test Cost Minimization for Hybrid Bist. [Citation Graph (0, 0)][DBLP]
   DFT, 2000, pp:283-291 [Conf]
   
5. Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
   Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment. [Citation Graph (0, 0)][DBLP]
   DSD, 2005, pp:83-87 [Conf]
   
6. Elmet Orasson, Rein Raidma, Raimund Ubar, Gert Jervan, Zebo Peng
   Fast Test Cost Calculation for Hybrid BIST in Digital Systems. [Citation Graph (0, 0)][DBLP]
   DSD, 2001, pp:318-325 [Conf]
   
7. Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
   A Hybrid BIST Architecture and Its Optimization for SoC Testing. [Citation Graph (0, 0)][DBLP]
   ISQED, 2002, pp:273-279 [Conf]
   
8. Gert Jervan, Anton Arhipov, Peeter Ellervee
   Work in Progress: FPGA Based Emulation Environment. [Citation Graph (0, 0)][DBLP]
   ReCoSoC, 2006, pp:146-151 [Conf]
   
9. Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
   Test Time Minimization for Hybrid BIST of Core-Based Systems. [Citation Graph (0, 0)][DBLP]
   J. Comput. Sci. Technol., 2006, v:21, n:6, pp:907-912 [Journal]
   
10. 
    Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. [Citation Graph (, )][DBLP]
    
    
11. 
    Hybrid BIST Optimization Using Reseeding and Test Set Compaction. [Citation Graph (, )][DBLP]
    
    
12. 
    Optimization of Memory-Constrained Hybrid BIST for Testing Core-Based Systems. [Citation Graph (, )][DBLP]