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Author:
Zebo Peng: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
    Hybrid BIST Test Scheduling Based on Defect Probabilities. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:230-235 [Conf]
  2. Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
    Test Time Minimization for Hybrid BIST of Core-Based Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:318-325 [Conf]
  3. Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng
    Integrated Test Scheduling, Test Parallelization and TAMDesign. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:397-404 [Conf]
  4. Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
    SOC Test Scheduling with Test Set Sharing and Broadcasting. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:162-169 [Conf]
  5. Erik Larsson, Zebo Peng
    Test Scheduling and Scan-Chain Division under Power Constraint. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:259-264 [Conf]
  6. Julien Pouget, Erik Larsson, Zebo Peng
    SOC Test Time Minimization Under Multiple Constraints. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:312-317 [Conf]
  7. Petru Eles, Zebo Peng, Alexa Doboli
    VHDL system-level specification and partitioning in a hardware/software co-synthesis environment. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:49-55 [Conf]
  8. Paul Pop, Petru Eles, Zebo Peng
    Performance estimation for embedded systems with data and control dependencies. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:62-66 [Conf]
  9. Traian Pop, Petru Eles, Zebo Peng
    Holistic scheduling and analysis of mixed time/event-triggered distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:187-192 [Conf]
  10. Traian Pop, Petru Eles, Zebo Peng
    Design optimization of mixed time/event-triggered distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:83-89 [Conf]
  11. Paul Pop, Petru Eles, Zebo Peng
    Scheduling with optimized communication for time-triggered embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:178-182 [Conf]
  12. Paul Pop, Petru Eles, Traian Pop, Zebo Peng
    Minimizing system modification in an incremental design approach. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:183-188 [Conf]
  13. Mauricio Varea, Bashir M. Al-Hashimi, Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Symbolic model checking of Dual Transition Petri Nets. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:43-48 [Conf]
  14. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Quasi-static assignment of voltages and optional cycles for maximizing rewards in real-time systems with energy c-onstraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:889-894 [Conf]
  15. Sorin Manolache, Petru Eles, Zebo Peng
    Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:266-269 [Conf]
  16. Zebo Peng
    Synthesis of VLSI systems with the CAMAD design aid. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:278-284 [Conf]
  17. Paul Pop, Petru Eles, Traian Pop, Zebo Peng
    An Approach to Incremental Design of Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:450-455 [Conf]
  18. Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi
    Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:518-525 [Conf]
  19. Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi
    Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:514-519 [Conf]
  20. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Quasi-Static Scheduling for Real-Time Systems with Hard and Soft Tasks. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1176-1183 [Conf]
  21. Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop
    Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:132-0 [Conf]
  22. Zhiyuan He, Zebo Peng, Petru Eles
    Power constrained and defect-probability driven SoC test scheduling with test set partitioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:291-296 [Conf]
  23. Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng
    Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:864-869 [Conf]
  24. Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng
    Synthesis of fault-tolerant schedules with transparency/performance trade-offs for distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:706-711 [Conf]
  25. Daniel Karlsson, Petru Eles, Zebo Peng
    Formal verification of systemc designs using a petri-net based representation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1228-1233 [Conf]
  26. Erik Larsson, Zebo Peng
    An integrated system-on-chip test framework. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:138-144 [Conf]
  27. Sorin Manolache, Petru Eles, Zebo Peng
    Buffer space optimisation with communication synthesis and traffic shaping for NoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:718-723 [Conf]
  28. Paul Pop, Petru Eles, Zebo Peng
    Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:567-0 [Conf]
  29. Paul Pop, Petru Eles, Zebo Peng
    Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10184-10189 [Conf]
  30. Paul Pop, Petru Eles, Zebo Peng, Viacheslav Izosimov, Magnus Hellring, Olof Bridal
    Design Optimization of Multi-Cluster Embedded Systems for Real-Time Application. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1027-1033 [Conf]
  31. Raimund Ubar, Artur Jutman, Zebo Peng
    Timing simulation of digital circuits with binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:460-466 [Conf]
  32. Laurence Tianruo Yang, Zebo Peng
    An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:74-81 [Conf]
  33. Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
    A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:61-66 [Conf]
  34. Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng
    Synthesis of Fault-Tolerant Embedded Systems with Checkpointing and Replication. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:440-447 [Conf]
  35. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Static Scheduling of Monoprocessor Real-Time Systems composed of Hard and Soft Tasks. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:115-120 [Conf]
  36. Abdil Rashid Mohamed, Zebo Peng, Petru Eles
    A Wiring-Aware Approach to Minimizing Built-in Self-Test Overhead. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:413-415 [Conf]
  37. Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
    Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:225-0 [Conf]
  38. Gert Jervan, Zebo Peng, Raimund Ubar
    Test Cost Minimization for Hybrid Bist. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:283-291 [Conf]
  39. Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
    Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:385-392 [Conf]
  40. Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi
    Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:477-485 [Conf]
  41. Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
    Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:83-87 [Conf]
  42. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Hierarchical Modeling and Verification of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:63-71 [Conf]
  43. Daniel Karlsson, Petru Eles, Zebo Peng
    A Formal Verification Methodology for IP-based Designs. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:372-379 [Conf]
  44. Daniel Karlsson, Petru Eles, Zebo Peng
    Validation of Embedded Systems Using Formal Method Aided Simulation. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:196-201 [Conf]
  45. Elmet Orasson, Rein Raidma, Raimund Ubar, Gert Jervan, Zebo Peng
    Fast Test Cost Calculation for Hybrid BIST in Digital Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:318-325 [Conf]
  46. Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
    Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:403-411 [Conf]
  47. Abdil Rashid Mohamed, Zebo Peng, Petru Eles
    A Heuristic for Wiring-Aware Built-In Self-Test Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:408-415 [Conf]
  48. André Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng
    Integrated Design and Test Generation Under Internet Based Environment MOSCITO. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:187-195 [Conf]
  49. Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng
    Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems*. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:313-322 [Conf]
  50. Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng
    Off-Line Testing of Delay Faults in NoC Interconnects. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:677-680 [Conf]
  51. Sorin Manolache, Petru Eles, Zebo Peng
    Memory and Time-Efficient Schedulability Analysis of Task Sets with Stochastic Execution Time. [Citation Graph (0, 0)][DBLP]
    ECRTS, 2001, pp:19-0 [Conf]
  52. Traian Pop, Petru Eles, Zebo Peng
    Schedulability Analysis for Distributed Heterogeneous Time/Event Triggered Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    ECRTS, 2003, pp:257-266 [Conf]
  53. Paul Pop, Petru Eles, Zebo Peng, Viacheslav Izosimov
    Schedulability-Driven Partitioning and Mapping for Multi-Cluster Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    ECRTS, 2004, pp:91-100 [Conf]
  54. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Formal Coverification of Embedded Systems Using Model Checking. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1106-1113 [Conf]
  55. Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop
    Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10168-0 [Conf]
  56. Peter Grün, Petru Eles, Krzysztof Kuchcinski, Zebo Peng
    Automatic Parallelization of a Petri Net-Based Design Representation for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1996, pp:185-192 [Conf]
  57. Jonas Hallberg, Zebo Peng
    Estimation and Consideration of Interconnection Delays during High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10349-10356 [Conf]
  58. Paul Pop, Petru Eles, Zebo Peng
    An Improved Scheduling Technique for Time-Triggered Embedded Systems. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1303-1310 [Conf]
  59. Laurence Tianruo Yang, Zebo Peng
    An Improved Register-Transfer Level Functional Partitioning Approach for Testability. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10107-0 [Conf]
  60. Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi
    Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:362-369 [Conf]
  61. Erik Larsson, Zebo Peng, Gunnar Carlsson
    The Design and Optimization of SOC Test Solutions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:523-530 [Conf]
  62. Sorin Manolache, Petru Eles, Zebo Peng
    Schedulability analysis of multiprocessor real-time applications with stochastic task execution times. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:699-706 [Conf]
  63. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Definitions of Equivalence for Transformational Synthesis of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICECCS, 2000, pp:134-142 [Conf]
  64. Zebo Peng
    Semantics of a Parallel Computation Model and its Applications in Digital Hardware Design. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:69-73 [Conf]
  65. Zebo Peng
    Construction of Asynchronous Concurrent Systems from their Behavioral Specifications. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1986, pp:859-864 [Conf]
  66. Erik Stoy, Zebo Peng
    An Integrated Modelling Technique for Hardware/Software Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:399-402 [Conf]
  67. Razvan Jigorea, Sorin Manolache, Petru Eles, Zebo Peng
    Modeling of Real-Time Embedded Systems in an Object-Oriented Design Environment with UML. [Citation Graph (0, 0)][DBLP]
    ISORC, 2000, pp:210-0 [Conf]
  68. Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
    A Hybrid BIST Architecture and Its Optimization for SoC Testing. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:273-279 [Conf]
  69. Petru Eles, Zebo Peng, Krzysztof Kuchcinski, Alex Doboli
    Hardware/Software Partitioning with Iterative Improvement Heuristics. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:71-76 [Conf]
  70. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Verification of Embedded Systems using a Petri Net based Representation. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:149-156 [Conf]
  71. Petru Eles, Zebo Peng, Daniel Karlsson
    Formal Verification in a Component-Based Reuse Methodology. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:156-161 [Conf]
  72. Xinli Gu, Krzysztof Kuchcinski, Zebo Peng
    An Efficient and Economic Partitioning Approach for Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:403-412 [Conf]
  73. Erik Larsson, Zebo Peng
    A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1135-1144 [Conf]
  74. Paul Pop, Petru Eles, Zebo Peng
    Schedulability-driven frame packing for multi-cluster distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    LCTES, 2003, pp:113-122 [Conf]
  75. Sorin Manolache, Petru Eles, Zebo Peng
    Optimization of Soft Real-Time Systems with Deadline Miss Ratio Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time and Embedded Technology and Applications Symposium, 2004, pp:562-570 [Conf]
  76. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Quasi-Static Scheduling for Multiprocessor Real-Time Systems with Hard and Soft Tasks. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2005, pp:422-428 [Conf]
  77. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    A Quasi-Static Approach to Minimizing Energy Consumption in Real-Time Systems under Reward Constraints. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2006, pp:279-286 [Conf]
  78. Paul Pop, Petru Eles, Zebo Peng
    Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems. [Citation Graph (0, 0)][DBLP]
    RTCSA, 1999, pp:287-294 [Conf]
  79. Traian Pop, Paul Pop, Petru Eles, Zebo Peng
    Optimization of Hierarchically Scheduled Heterogeneous Embedded Systems. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2005, pp:67-71 [Conf]
  80. Erik Larsson, Julien Pouget, Zebo Peng
    Defect-Aware SOC Test Scheduling. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:361-366 [Conf]
  81. Petru Eles, Krzysztof Kuchcinski, Zebo Peng
    Synthesis of systems specified as interacting VHDL processes. [Citation Graph (0, 0)][DBLP]
    Integration, 1996, v:21, n:1-2, pp:113-138 [Journal]
  82. Abdil Rashid Mohamed, Zebo Peng, Petru Eles
    A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:216-223 [Journal]
  83. Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
    Test Time Minimization for Hybrid BIST of Core-Based Systems. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2006, v:21, n:6, pp:907-912 [Journal]
  84. Erik Stoy, Zebo Peng
    Inter-domain movement of functionality as a repartitioning strategy for hardware/software co-design. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 1997, v:43, n:1-5, pp:87-98 [Journal]
  85. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Modeling and formal verification of embedded systems based on a Petri net representation. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:571-598 [Journal]
  86. Paul Pop, Petru Eles, Zebo Peng
    Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 2004, v:26, n:3, pp:297-325 [Journal]
  87. Erik Larsson, Zebo Peng
    Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:227-239 [Journal]
  88. Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng
    Efficient test solutions for core-based designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:758-775 [Journal]
  89. Zebo Peng, Krzysztof Kuchcinski
    Automated transformation of algorithms into register-transfer level implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:150-166 [Journal]
  90. Paul Pop, Petru Eles, Zebo Peng
    Schedulability-driven frame packing for multicluster distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:1, pp:112-140 [Journal]
  91. Mauricio Varea, Bashir M. Al-Hashimi, Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Dual Flow Nets: Modeling the control/data-flow relation in embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:1, pp:54-81 [Journal]
  92. Sorin Manolache, Petru Eles, Zebo Peng
    Schedulability analysis of applications with stochastic task execution times. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:4, pp:706-735 [Journal]
  93. Paul Pop, Petru Eles, Zebo Peng, Traian Pop
    Analysis and optimization of distributed real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:3, pp:593-625 [Journal]
  94. Paul Pop, Petru Eles, Zebo Peng, Traian Pop
    Scheduling and mapping in an incremental design methodology for distributed real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:8, pp:793-811 [Journal]
  95. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Quasi-Static Assignment of Voltages and Optional Cycles in Imprecise-Computation Systems With Energy Considerations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:10, pp:1117-1129 [Journal]
  96. Traian Pop, Paul Pop, Petru Eles, Zebo Peng
    Bus access optimisation for FlexRay-based distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:51-56 [Conf]
  97. Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
    Optimized integration of test compression and sharing for SOC testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:207-212 [Conf]
  98. Sorin Manolache, Petru Eles, Zebo Peng
    Fault-aware Communication Mapping for NoCs with Guaranteed Latency. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2007, v:35, n:2, pp:125-156 [Journal]
  99. Alexandru Andrei, Petru Eles, Zebo Peng, Marcus T. Schmitz, Bashir M. Al-Hashimi
    Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:262-275 [Journal]
  100. Petru Eles, Alex Doboli, Paul Pop, Zebo Peng
    Scheduling with bus access optimization for distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:472-491 [Journal]
  101. Erik Larsson, Julien Pouget, Zebo Peng
    Abort-on-Fail Based Test Scheduling. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:6, pp:651-658 [Journal]
  102. Julien Pouget, Erik Larsson, Zebo Peng
    Multiple-Constraint Driven System-on-Chip Test Time Optimization. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:6, pp:599-611 [Journal]

  103. On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration. [Citation Graph (, )][DBLP]


  104. Quality-driven synthesis of embedded multi-mode control systems. [Citation Graph (, )][DBLP]


  105. Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns. [Citation Graph (, )][DBLP]


  106. Synthesis of Fault-Tolerant Embedded Systems. [Citation Graph (, )][DBLP]


  107. A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems. [Citation Graph (, )][DBLP]


  108. Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints. [Citation Graph (, )][DBLP]


  109. Temperature-Aware Voltage Selection for Energy Optimization. [Citation Graph (, )][DBLP]


  110. A controller testability analysis and enhancement technique. [Citation Graph (, )][DBLP]


  111. Integrated scheduling and synthesis of control applications on distributed embedded systems. [Citation Graph (, )][DBLP]


  112. Analysis and optimization of fault-tolerant embedded systems with hardened processors. [Citation Graph (, )][DBLP]


  113. Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling. [Citation Graph (, )][DBLP]


  114. Multi-temperature testing for core-based system-on-chip. [Citation Graph (, )][DBLP]


  115. Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling. [Citation Graph (, )][DBLP]


  116. Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time Systems. [Citation Graph (, )][DBLP]


  117. Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment. [Citation Graph (, )][DBLP]


  118. Timing Analysis of the FlexRay Communication Protocol. [Citation Graph (, )][DBLP]


  119. Schedulability analysis for systems with data and control dependencies. [Citation Graph (, )][DBLP]


  120. Timing constraint specification and synthesis in behavioral VHDL. [Citation Graph (, )][DBLP]


  121. Testability analysis and improvement from VHDL behavioral specifications. [Citation Graph (, )][DBLP]


  122. Synthesis of VHDL concurrent processes. [Citation Graph (, )][DBLP]


  123. Immune Genetic Algorithms for Optimization of Task Priorities and FlexRay Frame Identifiers. [Citation Graph (, )][DBLP]


  124. Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip. [Citation Graph (, )][DBLP]


  125. Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip. [Citation Graph (, )][DBLP]


  126. Transactor-based Formal Verification of Real-time Embedded Systems. [Citation Graph (, )][DBLP]


  127. A Formal Verification Approach for IP-based Designs. [Citation Graph (, )][DBLP]


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