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Publications of Author

1. Chih Wei Hu, Chung-Len Lee, Wen Ching Wu, Jwu E. Chen
   Fault diagnosis of odd-even sorting networks. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1997, pp:288-0 [Conf]
   
2. Wen Ching Wu, Chung-Len Lee, Jwu E. Chen
   Identification of robust untestable path delay faults. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1995, pp:229-0 [Conf]
   
3. Ming Shae Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu
   Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2005, pp:106-111 [Conf]
   
4. Wen Ching Wu, Chung-Len Lee
   A Probabilistic Testability Measure for Delay Faults. [Citation Graph (0, 0)][DBLP]
   DAC, 1991, pp:440-445 [Conf]
   
5. Wen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin
   Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning. [Citation Graph (0, 0)][DBLP]
   EDAC-ETC-EUROASIC, 1994, pp:661- [Conf]
   
6. Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu
   MRAM Defect Analysis and Fault Modeli. [Citation Graph (0, 0)][DBLP]
   ITC, 2004, pp:124-133 [Conf]
   
7. Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu
   A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories. [Citation Graph (0, 0)][DBLP]
   MTDT, 2004, pp:65-69 [Conf]
   
8. Wen Ching Wu, Chung-Len Lee, Jwu E. Chen
   A Two-Phase Fault Simulation Scheme for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
   J. Inf. Sci. Eng., 1998, v:14, n:3, pp:669-686 [Journal]