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Publications of Author

1. Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee
   Built-in current sensor designs based on the bulk-driven technique. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1997, pp:384-0 [Conf]
   
2. Tsung-Chu Huang, Kuen-Jong Lee
   A Low-Power LFSR Architecture. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2001, pp:470- [Conf]
   
3. Tsung-Chu Huang, Kuen-Jong Lee
   An Input Control Technique for Power Reduction in Scan Circuits During Test Application. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1999, pp:315-320 [Conf]
   
4. Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen
   Peak-power reduction for multiple-scan circuits during test application. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2000, pp:453-458 [Conf]
   
5. Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai
   Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1996, pp:100-0 [Conf]
   
6. Tsung-Chu Huang, Kuen-Jong Lee
   A token scan architecture for low power testing. [Citation Graph (0, 0)][DBLP]
   ITC, 2001, pp:660-669 [Conf]
   
7. Tsung-Chu Huang, Kuen-Jong Lee
   Reduction of power consumption in scan-based circuits during testapplication by an input control technique. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:911-917 [Journal]
   
8. Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang
   BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:2, pp:194-218 [Journal]
   
9. Tsung-Chu Huang, Gau-Bin Chang, Ling Li
   Congruence Synchronous Mirror Delay. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:2184-2187 [Conf]