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Kuen-Jong Lee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee
    Built-in current sensor designs based on the bulk-driven technique. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:384-0 [Conf]
  2. Tsung-Chu Huang, Kuen-Jong Lee
    A Low-Power LFSR Architecture. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:470- [Conf]
  3. Tsung-Chu Huang, Kuen-Jong Lee
    An Input Control Technique for Power Reduction in Scan Circuits During Test Application. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:315-320 [Conf]
  4. Chih-Haur Huang, Kuen-Jong Lee, Soon-Jyh Chang
    A Low-Cost Diagnosis Methodology for Pipelined A/D Converters. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:296-301 [Conf]
  5. Kuen-Jong Lee, Jih-Jeen Chen
    Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:338-0 [Conf]
  6. Kuen-Jong Lee, Soon-Jyh Chang, Ruei-Shiuan Tzeng
    A Sigma-Delta Modulation Based BIST Scheme for A/D Converters. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:124-129 [Conf]
  7. Kuen-Jong Lee, Cheng-I. Huang
    A hierarchical test control architecture for core based design. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:248-253 [Conf]
  8. Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen
    Peak-power reduction for multiple-scan circuits during test application. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:453-458 [Conf]
  9. Kuen-Jong Lee, Shaing-Jer Hsu, Chia-Ming Ho
    Test Power Reduction with Multiple Capture Orders. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:26-31 [Conf]
  10. Kuen-Jong Lee, Jing-Jou Tang
    Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:165-171 [Conf]
  11. Kuen-Jong Lee, Jing-Jou Tang, Wern-Yih Duh
    On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:113-118 [Conf]
  12. Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai
    Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:100-0 [Conf]
  13. Wei-Lun Wang, Kuen-Jong Lee
    Accelerated test pattern generators for mixed-mode BIST environments. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:368-373 [Conf]
  14. Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
    SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:26-29 [Conf]
  15. Yun-Che Wen, Kuen-Jong Lee
    An on Chip ADC Test Structure. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:221-225 [Conf]
  16. Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang
    Using a single input to support multiple scan chains. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:74-78 [Conf]
  17. Kuen-Jong Lee, Rajiv Gupta, Melvin A. Breuer
    A New Method for Assigning Signal Flow Directions to MOS Transistors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:492-495 [Conf]
  18. Kuen-Jong Lee, Chia-Yi Chu, Yu-Ting Hong
    An embedded processor based SOC test platform. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2983-2986 [Conf]
  19. Kuen-Jong Lee, Sheng-Yih Jeng, Tian-Pao Lee
    A New Architecture for Analog Boundary Scan. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:409-412 [Conf]
  20. Jing-Jou Tang, Bin-Da Liu, Kuen-Jong Lee
    An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs). [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:393-396 [Conf]
  21. Tsung-Chu Huang, Kuen-Jong Lee
    A token scan architecture for low power testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:660-669 [Conf]
  22. Wei-Lun Wang, Jhing-Fa Wang, Kuen-Jong Lee
    A Fast Testing Method for Sequential Circuits at the State Trasition Level. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:514-519 [Conf]
  23. Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
    An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:130-135 [Conf]
  24. Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, K. J. Lee
    An Efficient BIST Method for Small Buffers. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:246-251 [Conf]
  25. Kuen-Jong Lee, Cheng-Hsuing Kuo
    Concurrent Error Detection, Diagnosis, and Fault Tolerance for Switched-Capacitor Filters. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:4, pp:863-890 [Journal]
  26. Kuen-Jong Lee, Wei-Lun Wang, Jhing-Fa Wang
    A General Structure of Feedback Shift Registers for Built-In Self Test. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:3, pp:645-667 [Journal]
  27. Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee
    Test pattern generation and clock disabling for simultaneous test time and power reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:363-370 [Journal]
  28. Tsung-Chu Huang, Kuen-Jong Lee
    Reduction of power consumption in scan-based circuits during testapplication by an input control technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:911-917 [Journal]
  29. Kuen-Jong Lee, Melvin A. Breuer
    Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:659-670 [Journal]
  30. Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang
    Broadcasting test patterns to multiple circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1793-1802 [Journal]
  31. Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
    SWiTEST: a switch level test generation system for CMOS combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:625-637 [Journal]
  32. Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta, Melvin A. Breuer
    An integrated system for assigning signal flow directions to CMOS transistors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1445-1458 [Journal]
  33. Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu
    A graph representation for programmable logic arrays to facilitate testing and logic design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:1030-1043 [Journal]
  34. Yun-Che Wen, Kuen-Jong Lee
    Analysis and generation of control and observation structures foranalog circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:165-171 [Journal]
  35. Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang
    BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:2, pp:194-218 [Journal]
  36. Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
    Reduction of detected acceptable faults for yield improvement via error-tolerance. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1599-1604 [Conf]
  37. Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu
    A practical current sensing technique for IDDQ testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:302-310 [Journal]
  38. Wei-Lun Wang, Kuen-Jong Lee, Jhing-Fa Wang
    An on-chip march pattern generator for testing embedded memory cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:730-735 [Journal]

  39. Transaction Level Modeling and Design Space Exploration for SOC Test Architectures. [Citation Graph (, )][DBLP]


  40. A hybrid self-testing methodology of processor cores. [Citation Graph (, )][DBLP]


  41. A hybrid software-based self-testing methodology for embedded processor. [Citation Graph (, )][DBLP]


  42. Full System Simulation and Verification Framework. [Citation Graph (, )][DBLP]


  43. Turbo1500: Core-Based Design for Test and Diagnosis. [Citation Graph (, )][DBLP]


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