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Soon-Jyh Chang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chih-Haur Huang, Kuen-Jong Lee, Soon-Jyh Chang
    A Low-Cost Diagnosis Methodology for Pipelined A/D Converters. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:296-301 [Conf]
  2. Kuen-Jong Lee, Soon-Jyh Chang, Ruei-Shiuan Tzeng
    A Sigma-Delta Modulation Based BIST Scheme for A/D Converters. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:124-129 [Conf]
  3. Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang
    A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:52-57 [Conf]
  4. Soon Jyh Chang, Chung-Len Lee, Jwu E. Chen
    Functional test pattern generation for CMOS operational amplifier. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:267-273 [Conf]
  5. Jin-Fu Lin, Soon-Jyh Chang
    A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  6. Yen-Ting Liu, Lih-Yih Chiou, Soon-Jyh Chang
    Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  7. A Jitter Characterizing BIST with Pulse-Amplifying Technique. [Citation Graph (, )][DBLP]


  8. Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique. [Citation Graph (, )][DBLP]


  9. Performance-driven analog placement considering boundary constraint. [Citation Graph (, )][DBLP]


  10. An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders. [Citation Graph (, )][DBLP]


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