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Yeong-Jar Chang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang
    Fail Pattern Identification for Memory Built-In Self-Repair. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:366-371 [Conf]
  2. Ming Shae Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu
    Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:106-111 [Conf]
  3. Yeong-Jar Chang, Chung-Len Lee
    Synthesis of Multi-Variable MVL Funtions Using Hybrid Mode CMOS Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:35-41 [Conf]
  4. Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu
    MRAM Defect Analysis and Fault Modeli. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:124-133 [Conf]
  5. Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu
    A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:65-69 [Conf]
  6. Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su
    A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2000, v:16, n:5, pp:751-766 [Journal]

  7. Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. [Citation Graph (, )][DBLP]


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