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Eduardo J. Peralías: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José L. Huertas
    Testing mixed-signal cores: practical oscillation-based test in an analog macrocell. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:31-38 [Conf]
  2. Salvador Mir, Adoración Rueda, Thomas Olbrich, Eduardo J. Peralías, José Luis Huertas
    SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:281-286 [Conf]
  3. Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
    Digital Background Gain Error Correction in Pipeline ADCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:82-87 [Conf]
  4. Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda, Ralf Seepold, Natividad Martínez Madrid
    A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:310-315 [Conf]
  5. Natividad Martínez Madrid, Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda
    Analog/mixed-signal IP modeling for design reuse. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:766-767 [Conf]
  6. Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas
    A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:534-538 [Conf]
  7. Juan A. Prieto, Adoración Rueda, Ian A. Grout, Eduardo J. Peralías, José L. Huertas, Andrew M. D. Richardson
    An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:905-0 [Conf]
  8. Eduardo J. Peralías, Adoración Rueda, José Luis Huertas
    Statistical behavioral modeling and characterization of A/D converters. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:562-566 [Conf]
  9. Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
    Full calibration digital techniques for pipeline ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1976-1979 [Conf]
  10. Eduardo J. Peralías, Adoración Rueda, José L. Huertas
    Structural testing of pipelined analog to digital converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:436-439 [Conf]
  11. Eduardo J. Peralías, Adoración Rueda, Juan A. Prieto, José L. Huertas
    DfT and on-line test of high-performance data converters: a practical case. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:534-0 [Conf]
  12. Raúl Jiménez, Antonio J. Acosta, Eduardo J. Peralías, Adoración Rueda
    An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:295-305 [Conf]
  13. Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
    Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:317-322 [Conf]
  14. Eduardo J. Peralías, Gloria Huertas, Adoración Rueda, José L. Huertas
    Self-Testable Pipelined ADC with Low Hardware Overhead. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:272-278 [Conf]
  15. Eduardo J. Peralías, Adoración Rueda, José L. Huertas
    A DFT Technique for Analog-to-Digital Converters with digital correction. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:302-307 [Conf]
  16. Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José Luis Huertas
    Practical Oscillation-Based Test of Integrated Filters. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:6, pp:64-72 [Journal]
  17. Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José Luis Huertas
    Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:6, pp:73-82 [Journal]
  18. Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
    Improved Background Algorithms for Pipeline ADC Full Calibration. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3383-3386 [Conf]
  19. Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
    Statistical analysis of a background correlation-based technique for full calibration of pipeline ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  20. Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS. [Citation Graph (, )][DBLP]


  21. A 2.4GHz LNA in a 90-nm CMOS technology designed with ACM model. [Citation Graph (, )][DBLP]


  22. Phase noise - consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies. [Citation Graph (, )][DBLP]


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