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Mani Soma: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sam D. Huynh, Seongwon Kim, Mani Soma, Jinyan Zhang
    Dynamic Test Set Generation for Analog Circuits and Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:360-365 [Conf]
  2. Sam D. Huynh, Jinyan Zhang, Seongwon Kim, Giri Devarayanadurg, Mani Soma
    Efficient Test Set Design for Analog and Mixed-Signal Circuits and Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:239-0 [Conf]
  3. Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Hirobumi Musha
    Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devices. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:45-48 [Conf]
  4. Yong Je Lim, Kyung-Im Son, Heung-Joon Park, Mani Soma
    A Statistical Approach to the Estimation of Delay Dependent Switching Activities in CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:445-450 [Conf]
  5. David Bordoley, Hieu Nguyen, Mani Soma
    A statistical study of the effectiveness of BIST jitter measurement techniques. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:100-107 [Conf]
  6. Giri Devarayanadurg, Mani Soma
    Analytical fault modeling and static test generation for analog ICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:44-47 [Conf]
  7. Giri Devarayanadurg, Mani Soma
    Dynamic test signal design for analog ICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:627-630 [Conf]
  8. Sam D. Huynh, Seongwon Kim, Mani Soma, Jinyan Zhang
    Testability analysis and multi-frequency ATPG for analog circuits and systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:376-383 [Conf]
  9. Bryan Nelson, Mani Soma
    On-chip calibration technique for delay line based BIST jitter measurement. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:944-947 [Conf]
  10. Thomas M. Bocek, Tuyen D. Vu, Mani Soma, Jason D. Moffatt
    Experimental Results for Current-Based Analog Scan. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:768-775 [Conf]
  11. Anchada Charoenrook, Mani Soma
    Fault Diagnosis of Flash ADC using DNL Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:680-689 [Conf]
  12. Giri Devarayanadurg, Prashant Goteti, Mani Soma
    Hierarchy Based Statistical Fault Simulation of Mixed-Signal ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:521-527 [Conf]
  13. Bozena Kaminska, Karim Arabi, I. Bell, José L. Huertas, B. Kim, Adoración Rueda, Mani Soma, Prashant Goteti
    Analog and Mixed-Signal Benchmark Circuits-First Release. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:183-190 [Conf]
  14. Mehdi Katoozi, Mani Soma
    A BIST Design of Structured Arrays with Fault-Tolerant Layout. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:514-521 [Conf]
  15. Seongwon Kim, Mani Soma
    Test evaluation and data on defect-oriented BIST architecture for high-speed PLL. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:830-837 [Conf]
  16. Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz
    CMOS Built-In Test Architecture for High-Speed Jitter Measurement. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:67-76 [Conf]
  17. Cecilia Metra, Flavio Giovanelli, Mani Soma, Bruno Riccò
    Self-checking scheme for very fast clocks' skew correction. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:652-661 [Conf]
  18. William H. Nicholls, Mani Soma
    Fault Bundling: Reducing Machine Evaluation Activity in Hierarchical Concurrent Fault Simulation. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:569-573 [Conf]
  19. Mani Soma
    Fault Coverage of DC Parametric Tests for Embedded Analog Amplifiers. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:566-573 [Conf]
  20. Mani Soma
    Panel Statement: Increasing test coverage in a VLSI design course. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1136- [Conf]
  21. Mani Soma, Welela Haileselassie, Jessica Yan, Rajesh Raina
    A Wavelet-Based Timing Parameter Extraction Method. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:120-128 [Conf]
  22. Karen Taylor, Bryan Nelson, Alan Chong, Hieu Nguyen, Henry C. Lin, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz
    Experimental Results for High-Speed Jitter Measurement Technique. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:85-94 [Conf]
  23. Takahiro J. Yamaguchi, Masahiro Ishida, Kiyotaka Ichiyama, Mani Soma, Christian Krawinkel, Katsuaki Ohsawa, Masao Sugai
    A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:77-84 [Conf]
  24. Takahiro J. Yamaguchi, Mani Soma
    Dynamic Testing of ADCs Using Wavelet Transforms. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:379-388 [Conf]
  25. Takahiro J. Yamaguchi, Mani Soma, David Halter, Jim Nissen, Rajesh Raina, Masahiro Ishida, Toshifumi Watanabe
    Jitter measurements of a PowerPCTM microprocessor using an analytic signal method. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:955-964 [Conf]
  26. Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Makoto Kurosawa, Hirobumi Musha
    Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:58-66 [Conf]
  27. Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Hirobumi Musha, Louis Malarsie
    A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:717-725 [Conf]
  28. Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida
    Testing clock distribution circuits using an analytic signal method. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:323-331 [Conf]
  29. Henry Chang, Steve Dollens, Gordon Roberts, Charles E. Stroud, Mani Soma, Jacob A. Abraham
    Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them? [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:415-416 [Conf]
  30. Seongwon Kim, Mani Soma, Dilip Risbud
    An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:231-236 [Conf]
  31. Mani Soma, Welela Haileselassie, Jessica Sherrid
    Measurement of Phase and Frequency Variations in Radio-Frequency Signal. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:203-208 [Conf]
  32. Qi Wang, Mani Soma
    RF Front-end System Gain and Linearity Built-in Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:228-233 [Conf]
  33. Qi Wang, Yi Tang, Mani Soma
    GHz RF Front-end Bandwidth Time Domain Measurement. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:223-228 [Conf]
  34. Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, David Halter, Rajesh Raina, Jim Nissen
    A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:102-110 [Conf]
  35. Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha
    Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:207-212 [Conf]
  36. Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Toshifumi Watanabe, Tadahiro Ohmi
    Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic Signal Method. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:395-402 [Conf]
  37. Jinyan Zhang, Sam D. Huynh, Mani Soma
    A Test Point Insertion Algorithm for Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:319-325 [Conf]
  38. Mani Soma
    Guest Editor's Introduction: Mixing Analog and Digital Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:1, pp:6-7 [Journal]
  39. Mani Soma, Sam D. Huynh, Jinyan Zhang, Seongwon Kim, Giri Devarayanadurg
    Hierarchical ATPG for Analog Circuits and Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:1, pp:72-81 [Journal]
  40. Mani Soma
    Mixed-signal on-chip timing measurements. [Citation Graph (0, 0)][DBLP]
    Integration, 1998, v:26, n:1-2, pp:151-165 [Journal]
  41. Giri Devarayanadurg, Mani Soma, Prashant Goteti, Sam D. Huynh
    Test set selection for structural faults in analog IC's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:1026-1039 [Journal]
  42. Kianosh Rahimi, Mani Soma
    Layout driven synthesis of multiple scan chains. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:317-326 [Journal]
  43. Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida
    Skew measurements in clock distribution circuits using an analytic signal method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:997-1009 [Journal]
  44. Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma
    An On-Chip Delta-Time-to-Voltage Converter for Real-Time Measurement of Clock Jitter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2798-2801 [Conf]
  45. Yong Je Lim, Mani Soma
    Statistical estimation of delay-dependent switching activities in embedded CMOS combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:3, pp:309-319 [Journal]

  46. Enhancing industry participation in ISCAS and Circuits and Systems Society. [Citation Graph (, )][DBLP]


  47. A Time-Domain Method for Pseudo-Spectral Characterization. [Citation Graph (, )][DBLP]


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