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Michiko Inoue: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Michiko Inoue, Emil Gizdarski, Hideo Fujiwara
    A class of sequential circuits with combinational test generation complexity under single-fault assumption. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:398-403 [Conf]
  2. Michiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa, Hideo Fujiwara
    A High-Level Synthesis Method for Weakly Testable Data Paths. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:40-45 [Conf]
  3. Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara
    Test Synthesis for Datapaths Using Datapath-Controller Functions. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:294-299 [Conf]
  4. Kazuko Kambe, Michiko Inoue, Hideo Fujiwara
    Efficient Template Generation for Instruction-Based Self-Test of Processor Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:152-157 [Conf]
  5. Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki
    Efficient Constraint Extraction for Template-Based Processor Self-Test Generation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:444-449 [Conf]
  6. Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
    A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:5-12 [Conf]
  7. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Software-Based Delay Fault Testing of Processor Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:68-71 [Conf]
  8. Yuki Yoshikaw, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
    Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:254-259 [Conf]
  9. Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara
    Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:32-39 [Conf]
  10. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Testing Superscalar Processors in Functional Mode. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:747-750 [Conf]
  11. Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    A Layout Adjustment Problem for Disjoint Rectangles Preserving Orthogonal Order. [Citation Graph (0, 0)][DBLP]
    Graph Drawing, 1998, pp:183-197 [Conf]
  12. Michiko Inoue, Chikateru Jinno, Hideo Fujiwara
    An Extended Class of Sequential Circuits with Combinational Test Generation Complexity. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:200-205 [Conf]
  13. Yasuro Sato, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    A Snapshot Algorithm for Distributed Mobile Systems. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1996, pp:734-743 [Conf]
  14. Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa
    Parallelizability of Some P-Complete Problems. [Citation Graph (0, 0)][DBLP]
    IPDPS Workshops, 2000, pp:116-122 [Conf]
  15. Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    A Parallel Algorithm for Weighted Distance Transforms. [Citation Graph (0, 0)][DBLP]
    IPPS, 1997, pp:407-412 [Conf]
  16. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Instruction-based delay fault self-testing of pipelined processor cores. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5686-5689 [Conf]
  17. Akihiro Fujiwara, H. Katsuki, Michiko Inoue, Toshimitsu Masuzawa
    Parallel Selection Algorithms with Analysis on Clusters. [Citation Graph (0, 0)][DBLP]
    ISPAN, 1999, pp:388-393 [Conf]
  18. Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    Parallel Algorithms for All Nearest Neighbors of Binary Images on the BSP Model. [Citation Graph (0, 0)][DBLP]
    ISPAN, 1999, pp:394-399 [Conf]
  19. T. Yamada, Akihiro Fujiwara, Michiko Inoue
    COM (Cost Oriented Memory) Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:259- [Conf]
  20. Sen Moriya, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    SelfStabilizing WaitFree Clock Synchronization with Bounded Space. [Citation Graph (0, 0)][DBLP]
    OPODIS, 1998, pp:129-144 [Conf]
  21. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Instruction-Based Delay Fault Self-Testing of Processor Cores. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:933-0 [Conf]
  22. Michiko Inoue, Wei Chen
    Linear-Time Snapshot Using Multi-writer Multi-reader Registers. [Citation Graph (0, 0)][DBLP]
    WDAG, 1994, pp:130-140 [Conf]
  23. Michiko Inoue, Sen Moriya, Toshimitsu Masuzawa, Hideo Fujiwara
    Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System. [Citation Graph (0, 0)][DBLP]
    WDAG, 1997, pp:290-304 [Conf]
  24. Michiko Inoue, Shinya Umetani, Toshimitsu Masuzawa, Hideo Fujiwara
    Adaptive Long-Lived O(k2)-Renaming with O(k2) Steps. [Citation Graph (0, 0)][DBLP]
    DISC, 2001, pp:123-135 [Conf]
  25. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Delay Fault Testing of Processor Cores in Functional Mode. [Citation Graph (0, 0)][DBLP]
    IEICE Transactions, 2005, v:88, n:3, pp:610-618 [Journal]
  26. Michiko Inoue, Hideo Fujiwara
    An approach to test synthesis from higher level. [Citation Graph (0, 0)][DBLP]
    Integration, 1998, v:26, n:1-2, pp:101-116 [Journal]
  27. Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    A cost optimal parallel algorithm for weighted distance transforms. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1999, v:25, n:4, pp:405-416 [Journal]
  28. Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    A layout adjustment problem for disjoint rectangles preserving orthogonal order. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2002, v:33, n:2, pp:31-42 [Journal]
  29. Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    Parallel algorithms for selection on the BSP and BSP* models. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2002, v:33, n:12, pp:97-107 [Journal]
  30. Chikara Ohori, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    A causal broadcast protocol for distributed mobile systems. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2001, v:32, n:3, pp:65-75 [Journal]
  31. Katsuyuki Takabatake, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    Non-scan design for testable data paths using thru operation. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1997, v:28, n:10, pp:60-68 [Journal]
  32. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1203-1215 [Journal]

  33. Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms. [Citation Graph (, )][DBLP]


  34. Partial Scan Approach for Secret Information Protection. [Citation Graph (, )][DBLP]


  35. Test pattern selection to optimize delay test quality with a limited size of test set. [Citation Graph (, )][DBLP]


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